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5228-ds09-405-r 16215 alton parkway ? p.o. box 57013 irvine, ca 92619-7013 phone: 949-450-8700 fax: 949-450-8710 7/12/04 data sheet BCM5228 10/100base-tx/fx octal- ? transceiver figure 1: functional block diagram g eneral description f eatures the BCM5228 is an octal 10/100base-tx/fx transceiver targeted at fast ethernet switches. the device contains eight fu ll-duplex 10base-t/100base- tx/fx fast ethernet transceivers, each of which perform all of the physical layer interface functions for 10base-t ethernet on category 3, 4, or 5 unshielded twisted-pair (utp) cable and 100base-tx fast ethernet on category 5 utp cable. the 100base-fx is supported at each port through the use of external fiber- optic transmit and receive devices. the BCM5228 is a highly integrated solution combining digital adaptive equalizers, adcs, phase locked loops, line drivers, encoders, decoders, and the required support circuitry into a single monolithic cmos chip. the BCM5228 complies with the ieee 802.3 specification, including the auto-negotiation subsections. the effective use of digital technology in the BCM5228 design results in robust performance over a broad range of operating scenarios. problems inherent to mixed- signal implementations (such as analog offset and on- chip noise) are eliminated by employing field-proven digital adaptive equalization and digital clock recovery techniques. 10base-t/100base-tx/fx ieee 802.3u compliant single-chip octal physical interface-rmii to magnetics reduced media independent interface (rmii) option-serial media independent interface (smii) option-source synchronous smii (s3mii) fully integrated digital adaptive equalizers 125-mhz clock generator and timing recovery on-chip multimode transmit waveshaping edge-rate control eliminates external filters integrated baseline wander correction hp auto-mdix cable length indication cable noise level indication ieee 802.3 -compliant auto-negotiation shared mii management interface up to 25 mbps serial led status pins programmable parallel led pins interrupt output capability loopback mode for diagnostics ieee 1149.1 (jtag) and nand chain ict support low-power, dual-supply 2.5v/3.3v cmos technology compatible with 2.5v/3.3v i/o 208-pin pqfp and 256-pin fpbga packages a pplications fast ethernet switches mii mii equalizer auto-negotiation led/int clock bias registers mgmt control correction /link integrity generator generator wander baseline 8 rxd{1:8} mdc mdio modes/controls td {1:8} rd {1:8} ref_clk recovery xmt dac crs/link detection adc led2{1:8} sssmii_dis/sled_clk multimode jtag test logic 5 jtag digital adaptive 10base-t pcs 100base-x pcs drivers clock 13 8 intr/sled_do led1{1:8} 8 8 txd{1:8} rdac ssync sssmii_txc sssmii_rsync auto- mdix sssmii_rxc
BCM5228 data sheet 7/12/04 broadcom corporation page ii document 5228-ds09-405-r r evision h istory revision date change description 5228-ds09-405-r 07/12/04 resized the ?bga pinout (top view)? figure to improve readability. 5228-ds08-r 06/02/03 added 2.5v i/o-ovdd option under ?features? on the cover. added ?hp auto-mdix.? added sled_clk frequency to ?serial led mode.? added description to bit 4, activity led, in table 37, ?auxiliary mode register (address 29d, 1dh).? 5228-ds07-r 09/09/02 added pll vdd pin definition table and figures. included details on isolate mode, super isolate mode, and auto power-down mode. included bit 15 (fdx led enable) changes to serial led mode. included jumbo packet mode bits and descriptions. show correct default value for shadow register 1ah. 5228-ds06-r 03/07/02 updated the following: ?mii register map summary? table. ?clock and reset timing? figure. ?packaging thermal characteristics? section. ?ordering information? section. 5228-ds05-r 10/24/01 added ordering information; added minor table information updates. 5228-ds04-r 03/15/01 added the following to ?features? on the cover: - option-source synchronous smii (s3mii) -hp auto-mdix - cable length indication - cable noise level indication following table 32, deleted from interrupt enable description: ?bits 14 and 15 of this register are mutually exclusive. only one may be set at a time.? in table 49, inserted typ values for parameters td after txen assert and txd to td steady state delay. in table 50, added typ values for parameter crs_dv assert after rd, crs_dv deassert after rd; and crs_dv deassert after rd, valid eop. deleted last row (parameter rd to crs_dv steady state delay). in table 57, added typ and max values for total supply current for avdd, dvdd and ovdd pins. added section 10: ?packaging thermal characteristics.? corrected specification of register 19h, bit 0 from jabber detect to full-duplex indication .
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r page iii 5228-ds03-r 09/01/00 correct several signal name inconsistencies. changed p14 from pllvddp to ovdd in: - tables 2 and 3 - figures 1, 2, and 3 changed agnd from c05 to c06 in table 3. modified description for ?100base-fx mode?. changed led_clk to sled_clk for ?low-cost serial led mode.? changed address 1ah bit 15 in table 15 from fdx led enable to reserved . deleted fdx led enable bit description for table 32. added tx_er parameter to table 49. added crs_dv, rx_er, and note 3 to table 50. changed srd_delay to srx_delay in figure 8. deleted reference to ivdd in table 57. 5228-ds02-r 12/15/99 added mdix info. minor editorial changes. 5228-ds01-r 11/24/99 initial release. revision date change description
broadcom ? and the pulse logo are registered trademarks of bro adcom corporation and/or its subsidiaries in the united states and certain other countries. all other trademarks mentioned are the property of their respective owners. this data sheet (including, without limitation, the broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high risk application. broadcom provides this data sheet "as- is", without warranty of any kind. broadcom disclaims all warranties, expressed and implied, including, without limitation, the im plied warranties of merchantability, fitness for a particular purpose, and non-infringement. broadcom corporation p.o. box 57013 16215 alton parkway irvine, ca 92619-7013 ? 2004 by broadcom corporation all rights reserved printed in the u.s.a.
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r page v t able of c ontents section 1: functional description ...................................................................................... 1 overview ............................................................................................................................... ........................ 1 encoder/decoder ............................................................................................................................... .......... 1 link monitor ............................................................................................................................... ................... 2 carrier sense ............................................................................................................................... ................. 2 auto-negotiation ............................................................................................................................... ........... 3 digital adaptive equalizer .......................................................................................................................... 3 adc ............................................................................................................................... ................................ 3 digital clock recovery/generator .............................................................................................................. 3 baseline wander correction ....................................................................................................................... 3 multimode transmit dac ............................................................................................................................ 5 stream cipher ............................................................................................................................... ................ 5 far-end fault ............................................................................................................................... ................. 5 reduced media independent interface (rmii) ............................................................................................ 5 mii management ............................................................................................................................... ............ 6 serial media independent interface (smii) ................................................................................................. 6 interrupt mode ............................................................................................................................... ............... 7 section 2: hardware signal definition table ..................................................................... 9 section 3: pinout diagrams .............................................................................................. 19 section 4: operational description ..................................................................................25 resetting the BCM5228 ............................................................................................................................. 25 loopback mode ............................................................................................................................... ........... 25 full-duplex mode ............................................................................................................................... ........ 25 100base-fx mode ............................................................................................................................... ...... 25 10base-t mode ............................................................................................................................... .......... 26 isolate mode ............................................................................................................................... ................ 26 super isolate mode ............................................................................................................................... ..... 26 auto power-down mode ............................................................................................................................ 26 jumbo packet mode ............................................................................................................................... ... 27 phy address ............................................................................................................................... ............... 27 hp auto-mdix ............................................................................................................................... .............. 28
BCM5228 data sheet 7/12/04 broadcom corporation page vi document 5228-ds09-405-r section 5: led modes ....................................................................................................... 29 description ............................................................................................................................... ...................29 serial led mode ............................................................................................................................... ..........29 low-cost serial led mode ........................................................................................................................30 parallel led mode ............................................................................................................................... .......33 section 6: register summary .......................................................................................... 35 mii management interface: register programming .................................................................................35 mii register map summary....................................................................................................... ............37 mii status register ............................................................................................................................... ......41 phy identifier registers .............................................................................................................................42 auto-negotiation advertisement register ...............................................................................................43 auto-negotiation link partner (lp) ability register ...............................................................................44 auto-negotiation expansion register ......................................................................................................45 auto-negotiation next page register .......................................................................................................46 auto-negotiation link partner (lp) next page transmit register .........................................................47 100base-x auxiliary control register .....................................................................................................48 100base-x auxiliary status register .......................................................................................................49 100base-x receive error counter ...........................................................................................................50 100base-x false carrier sense counter .................................................................................................51 100base-x disconnect counter ...............................................................................................................51 auxiliary control/status register .............................................................................................................52 auxiliary status summary register ..........................................................................................................54 interrupt register ............................................................................................................................... .........55 auxiliary mode 2 register ..........................................................................................................................56 10base-t auxiliary error and general status register .........................................................................57 auxiliary mode register .............................................................................................................................60 auxiliary multiple phy register ................................................................................................................61 broadcom test register ............................................................................................................................62 auxiliary mode 4 (phy 1) register (shadow register) ...........................................................................63 auxiliary mode 4 (phy 2) register (shadow register) ...........................................................................64 auxiliary mode 4 (phy 3) register (shadow register) ...........................................................................65 auxiliary status 2 register (shadow register) ........................................................................................66 auxiliary status 3 register (shadow register) ........................................................................................67 auxiliary mode 3 register (shadow register) .........................................................................................68
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r page vii auxiliary status 4 register (shadow register) ....................................................................................... 69 section 7: timing and ac characteristics ...................................................................... 70 section 8: electrical characteristics ................................................................................ 76 section 9: mechanical information ................................................................................... 78 section 10: packaging thermal characteristics ............................................................. 80 section 11: application examples ................................................................................... 82 section 12: ordering information ..................................................................................... 87
BCM5228 data sheet 7/12/04 broadcom corporation page viii document 5228-ds09-405-r
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r page ix l ist of f igures figure 1: functional block diagram ............................................................................................. ........................i figure 2: BCM5228f pinout diagram .............................................................................................. ................ 19 figure 3: BCM5228u pinout diagram .............................................................................................. ................ 20 figure 4: bga pinout (top view) ................................................................................................ ..................... 21 figure 5: clock and reset timing ............................................................................................... ..................... 70 figure 6: rmii transmit packet timing .......................................................................................... .................. 71 figure 7: rmii receive packet timing ........................................................................................... .................. 72 figure 8: rmii receive packet with false carrier............................................................................... ............. 72 figure 9: smii/s3mii timing.................................................................................................... ......................... 73 figure 10: management interface timing......................................................................................... ................ 74 figure 11: management interface timing (with preamble suppression on).................................................... 74 figure 12: 208-pin pqfp package ................................................................................................ .................. 78 figure 13: 256-pin fine pitch bga (fpbga) package.............................................................................. ...... 79 figure 14: smii application .................................................................................................... .......................... 82 figure 15: smii application using source synchronous signals................................................................... ... 83 figure 16: switch application .................................................................................................. ......................... 85
BCM5228 data sheet 7/12/04 broadcom corporation page x document 5228-ds09-405-r
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r page xi l ist of t ables table 1: 4b5b encoding......................................................................................................... ............................ 4 table 2: pin definitions....................................................................................................... ................................ 9 table 3: bga ballout by signal name............................................................................................ .................. 22 table 4: receive fifo size select .............................................................................................. .................... 27 table 5: jumbo packet enable and descrambler lock timer ........................................................................ .27 table 6: serial led mode bit framing ........................................................................................... .................. 29 table 7: low-cost serial mode bank 1 led selection ............................................................................. ....... 30 table 8: low-cost serial mode bank 2 led selection ............................................................................. ....... 30 table 9: low-cost serial mode bank 3 led selection ............................................................................. ....... 31 table 10: low-cost serial mode bank 4 led selection ............................................................................ ...... 31 table 11: low-cost serial mode bank 5 led selection ............................................................................ ...... 31 table 12: low-cost serial mode bank 6 led selection ............................................................................ ...... 32 table 13: parallel led mode led1 selection..................................................................................... ............. 33 table 14: parallel led mode led2 selection..................................................................................... ............. 33 table 15: parallel led mode led3 selection..................................................................................... ............. 34 table 16: mii management frame format.......................................................................................... ............. 35 table 17: mii register map summary............................................................................................. ................. 37 table 18: mii shadow register map summary (mii register 1fh, bit7 = 1) .................................................... 38 table 19: mii control register (address 00d, 00h) .............................................................................. ............ 39 table 20: mii status register (address 01d, 01h) ............................................................................... ............ 41 table 21: phy identifier registers (addresses 02d and 03d, 02h and 03h).................................................... 42 table 22: auto-negotiation advertisement register (address 04d, 04h)......................................................... 43 table 23: auto-negotiation link partner ability register (address 05d, 05h) .................................................. 44 table 24: auto-negotiation expansion register (address 06d, 06h) ............................................................... 45 table 25: next page transmit register (address 07d, 07h)....................................................................... ..... 46 table 26: next page transmit register (address 08d, 08h)....................................................................... ..... 47 table 27: 100-base-x auxiliary control register (address 16d, 10h) ............................................................ 4 8 table 28: 100base-x auxiliary status register (address 17d, 11h)............................................................... 49 table 29: 100base-x receive error counter (address 18d, 12h) .................................................................. 5 0 table 30: 100base-x false carrier sense counter (address 19d, 13h) ........................................................ 51 table 31: 100base-x disconnect counter......................................................................................... ............. 51 table 32: auxiliary control/status register (address 24d, 18h) ................................................................. ..... 52
BCM5228 data sheet 7/12/04 broadcom corporation page xii document 5228-ds09-405-r table 33: auxiliary status summary register (address 25d, 19h) ................................................................. ..54 table 34: interrupt register (address 26d, 1ah) ................................................................................ ..............55 table 35: auxiliary mode 2 register (address 27d, 1bh) ......................................................................... ........56 table 36: 10base-t auxiliary error and general status register (address 28d, 1ch) ...................................57 table 37: auxiliary mode register (address 29d, 1dh) ........................................................................... .........60 table 38: auxiliary multiple phy register (address 30d, 1eh) ................................................................... .....61 table 39: broadcom test (address 31d, 1fh) ..................................................................................... .............62 table 40: auxiliary mode 4 (phy 1) register (shadow register 26d, 1ah) .....................................................63 table 41: auxiliary mode 4 (phy 2) register (shadow register 26d, 1ah) .....................................................64 table 42: auxiliary mode 4 (phy 3) register (shadow register 26d, 1ah) .....................................................65 table 43: auxiliary status 2 register (shadow register 27d, 1bh)............................................................... ...66 table 44: cable length......................................................................................................... ............................66 table 45: auxiliary status 3 register (shadow register 28d, 1ch)............................................................... ...67 table 46: auxiliary mode 3 register (shadow register 29d, 1dh)................................................................. ..68 table 47: current receive fifo size ............................................................................................ ...................68 table 48: auxiliary status 4 register (shadow register 30d, 1eh)............................................................... ...69 table 49: clock timing ......................................................................................................... ............................70 table 50: reset timing ......................................................................................................... ............................70 table 51: rmii transmit timing................................................................................................. .......................71 table 52: rmii receive timing.................................................................................................. .......................71 table 53: smii/s3mii timing .................................................................................................... ........................72 table 54: auto-negotiation timing .............................................................................................. .....................73 table 55: led timing ........................................................................................................... ............................73 table 56: mii management data interface timing................................................................................. ...........73 table 58: recommended operating conditions ..................................................................................... ..........76 table 59: electrical characteristics........................................................................................... ........................76 table 60: theta ja vs. airflow for the BCM5228b (256 fpbga) package ........................................................80 table 61: theta ja vs. airflow for the BCM5228f (208 pqfp) package...........................................................80 table 62: theta ja vs. airflow for the BCM5228u (208 pqfp) package ..........................................................80 table 63: theta ja vs. airflow for the BCM5228b with heat sink......................................................................87
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r functional description page 1 section 1: functional description o verview the BCM5228 is a single-chip device containing eight independent fast ethernet transceivers. each transceiver performs all of the physical layer interface functions for 100base-tx full-duplex or half-duplex ethernet on category 5 unshielded twisted-pair (utp) cable, and 10base-t full-duplex or half-dupl ex ethernet on category 3, 4, or 5 utp cable. each port can also be configured for 100base-fx full-dupl ex or half-duplex transmission over fiber-optic cabling when paired with an external fiber-optic line driver and receiver. the chip performs: 4b5b, mlt3, nrzi, and manchester encoding and decoding clock and data recovery stream cipher scrambling/descrambling digital adaptive equalization line transmission carrier sense and link integrity monitor auto-negotiation rmii, smii, s3mii, and management functions the BCM5228 can be connected to a mac through the rmii or smii on one side, and directly to the network media on the other side through either: isolation transformers for utp modes fiber-optic transmitter/receiver components for fx mode the BCM5228 is compliant with the ieee 802.3 standard. e ncoder /d ecoder in 100base-tx and 100base-fx modes, the BCM5228 transmits and receives a continuous data stream on twisted-pair or fiber-optic cable. when the rmii transmit enable pin is asserted, data from the transmit data pins is encoded into 5-bit code groups and inserted into the transmit data stream. the 4b5b encoding is shown in table 1 on page 4 . the transmit packet is encapsulated by replacing the first two nibbles of preamble with a start-of-stream delimiter (j/k codes) and appending an end-of-stream delimiter (t/r codes) to the end of the packet. the transmitter repeatedly sends the idle code group between packets. in tx mode, the encoded data stream is scrambled by a stream cipher block and then serialized and encoded into mlt3 signal levels. a multimode transmit dac is used to drive the mlt3 data onto the twisted-pair cable. in fx mode, the scrambling function is bypassed and the data is nrzi encoded. the multimode transmit dac drives differential positive ecl (pecl) levels to an external fiber-optic transmitter.
BCM5228 data sheet 7/12/04 broadcom corporation page 2 link monitor document 5228-ds09-405-r following baseline wander correction, adaptive equalization, an d clock recovery in tx mode, the receive data stream is converted from mlt3 to serial nrzi data. the nrzi data is descrambled by the stream cipher block and then deserialized and aligned into 5-bit code groups. in fx mode, the receive data stream differential pecl levels are sampled from the fiber-optic receiver. baseline wander correction, adaptive equalization, and stream cipher descramb ling functions are bypassed, and nrzi decoding is used instead of mlt3. the 5-bit code groups are decoded into 4-bit data nibbles, as shown in table 1 on page 4 . the start-of-stream delimiter is replaced with preamble nibbles, and the end-of-stream delimiter and idle codes are replaced with all zeros. the decoded data is driven onto the rmii/smii receive data pins. when an invalid code group is detected in the data stream, the BCM5228 asserts the rmii/smii rxer signal. the chip also asserts rxer for several other error conditions that improperly terminate the data stream. while rxer is asserted, the receive data pins are driven with a 01 for an invalid data reception and a 10 for a false carrier. in 10base-t mode, manchester encoding and decoding is pe rformed on the data stream. the multimode transmit dac performs pre-equalization for 100m of category 3 cable. l ink m onitor in 100base-tx mode, receive signal energy is detected by monitoring the receive pair for transitions in the signal level. signal levels are qualified using squelch detect circuits. when no signal or certain invalid signals are detected on the receiv e pair, the link monitor enters and remains in the link fail state where only idle codes are transmitted. when a valid signal is detected on the receive pair for a minimum period of time, the link monitor enters the link pass state and the transmit and receive functions are enabled. in 100base-fx mode, the external fiber-optic receiver performs the signal energy detection function and communicates this information directly to the BCM5228 through the differential sd pins. in 10base-t mode, a link-pulse detection circuit constantly monitors the rd pins for the presence of valid link pulses. c arrier s ense in dte mode, the carrier sense and receive data valid signals are multiplexed on the same pin. the carrier sense is asserted asynchronously on the crs_dv pin as soon as valid activity is detected in the receive data stream. loss of carrier results in the deassertion of crs_dv synchronous to the cycle of ref_clk that presents the first di-bit of a nibble onto rxd. if the phy has additional bits to be presented on rxd following the initial deassertion of crs_dv, the phy asserts crs_dv on cycles of ref_clk that present the second di-bit of each nibble, and deasserts crs_dv on cycles of ref_clk that present the first di-bit of each nibble. if carrier sense is asserted and a valid ssd is not detected immediately, rxer is asserted. a value of 2h (2 hex) is driven on the receive data pins to indicate false carrier sense. in 10base-t mode, carrier sense is asserted asynchronously on the crs pin when valid preamble activity is detected on the rd input pins.
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r auto-negotiation page 3 a uto -n egotiation the BCM5228 contains the ability to negotiate its mode of operation over the twisted-pair link using the auto-negotiation mechanism defined in the ieee 802.3u specification. auto-negotiation can be enabled or disabled by hardware or software control. when the auto-negotiation function is enabled, the BCM5228 automatically chooses its mode of operation by advertising its abilities and comparing them with those received from its link partner. the BCM5228 can be configured to advertise 100base-tx full-duplex and/or half-duplex and 10 base-t full-duplex and/or half-duplex. each transceiver negotiates independently with its link partner and chooses the highest level of operation available for its own link. d igital a daptive e qualizer the digital adaptive equalizer removes interzonal interference created by the transmission channel media. the equalizer accepts sampled unequalized data from the adc on each channel and produces equalized data. the BCM5228 achieves an optimum signal to noise ratio by using a combination of feed-forward equalization and decision-feedback equalization. this powerful technique achieves a 100base-tx ber of less than 1 x 10 -12 for transmission up to 100 meters on category 5 twisted-pair cable, even in harsh noise environments. the digital adaptive equalizers in the BCM5228 achieve performance close to theoretical limits. the all-digital nature of the design makes the performance very tolerant to on-chip noise. the fil ter coefficients are self adapting to any quality of cable or cable length. because of transmit pre-equalization in 10base-t mode and complete lack of isi in 100base-fx mode, the adaptive equalizer is bypassed in this mode of operation. adc each receive channel has its own 125-mhz analog to digital converter (adc). the adc samples the incoming data on the receive channel and produces a digital output. the output of the adc is fed to the digital adaptive equalizer. advanced analog circuit techniques achieve low offset, high power supply noise rejection, fast settling time, and low bit error rate (be r). d igital c lock r ecovery /g enerator the all-digital clock recovery and generator block creates all internal transmit and receive clocks. the transmit clocks are locked to the 50-mhz clock input, while the receive clocks are locked to the incoming data streams. clock recovery circuits optimized to mlt3, nrzi, and manchester encoding schemes are included for use with each of the three different operating modes. the input data streams are sampled by the recovered clock from each port and fed synchronously to the respective digital adaptive equalizer. b aseline w ander c orrection a 100base-tx data stream is not always dc balanced. because the receive signal must pass through a transformer, the dc offset of the differential receive input can wander. this effect, known as baseline wander, can greatly reduce the noise immunity of the receiver. the BCM5228 automatically compensates for baseline wander by removing the dc offset from the
BCM5228 data sheet 7/12/04 broadcom corporation page 4 baseline wander correction document 5228-ds09-405-r input signal, and thereby significantly reducing the chance of a receive symbol error. the baseline wander correction circuit is not required, and is therefore bypassed, in 10base-t and 100base-fx operating modes table 1: 4b5b encoding name 4b code 5b code meaning 0 0000 11110 data 0 1 0001 01001 data 1 2 0010 10100 data 2 3 0011 10101 data 3 4 0100 01010 data 4 5 0101 01011 data 5 6 0110 01110 data 6 7 0111 01111 data 7 8 1000 10010 data 8 9 1001 10011 data 9 a 1010 10110 data a b 1011 10111 data b c 1100 11010 data c d 1101 11011 data d e 1110 11100 data e f 1111 11101 data f i 0000 a a. treated as invalid code (mapped to 0111) when received in data field. 11111 idle j 0101 a 11000 start-of-stream delimiter, part 1 k 0101 a 10001 start-of-stream delimiter, part 2 t 0000 a 01101 end-of-stream delimiter, part 1 r 0000 a 00111 end-of-stream delimiter, part 2 h 1000 00100 transmit error (used to force signalling errors) v 0111 00000 invalid code v 0111 00001 invalid code v 0111 00010 invalid code v 0111 00011 invalid code v 0111 00101 invalid code v 0111 00110 invalid code v 0111 01000 invalid code v 0111 01100 invalid code v 0111 10000 invalid code v 0111 11001 invalid code
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r multimode transmit dac page 5 m ultimode t ransmit dac the multimode transmit digital to analog converter (dac) transmits mlt3-coded symbols in 100base-tx mode, nrzi- coded symbols in 100base-fx mode and manchester-coded symbols in 10base-t mode. it performs programmable edge- rate control in tx mode, which decreases unwanted high frequency signal components thus reducing emi. high-frequency pre-emphasis is performed in 10base-t mode, and no filterin g is performed in 100base-fx mode. the transmit dac utilizes a current drive output which is well balanced and produces very low noise transmit signals. pecl voltage levels are produced with resistive terminations in 100base-fx mode. s tream c ipher in 100base-tx mode, the transmit data stream is scrambled in or der to reduce radiated emissions on the twisted-pair cable. the data is scrambled by exclusive oring the nrzi signal with the output of an 11-bit wide linear feedback shift register (lfsr), which produces a 2047-bit non-repeating sequence. the scrambler reduces peak emissions by randomly spreading the signal energy over the transmit frequency range, and elim inating peaks at certain frequencies. signal energy is spread further by using unique seeds to generate a different non-repeating sequence for each of the eight ports. the receiver descrambles the incoming data stream by exclusive oring it with the same sequence generated at the transmitter. the descrambler detects the state of the transmit lfsr by looking for a sequence representing consecutive idle codes. the descrambler locks to the scrambler state after detecting a sufficient number of consecutive idle code-groups. the receiver does not attempt to decode the data stream unless the descrambler is locked. once locked, the descrambler continuously monitors the data stream to make sure that it has not lost synchronization. the receive data stream is expected to contain inter-packet idle periods. if the descrambler does not detect enough idle codes within 724 s, it becomes unlocked, and the receive decoder is disabled. if the receiver is put into token ring mode (see bit 10, register 1bh), the descrambler monitors the receiver for 5792 s before unlocking. the descrambler is always forced into the unlocked state when a link failure condition is detected. stream cipher scrambling/descrambling is not used in 100base-fx and 10base-t modes. f ar -e nd f ault auto-negotiation provides a remote fault capability for detection of asymmetric link failures. because auto-negotiation is not available for 100base-fx, the BCM5228 implements the ieee 802.3 standard far-end fault mechanism for the indication and detection of remote error conditions. if the far-end fault mechanism is enabled, a transceiver transmits the far-end fault indication whenever a receive channel failure is detected (signal detect is deasserted). each transceiver also continuously monitors the receive channel when a valid signal is present (signal detect asserted). when its link partner is indicating a remote error, the transceiver forces its link monitor into the link fail state and set the remote fault bit in the rmii status register. the far-end fault mechanism is on by default in 100base-fx mode, off by default in 100base-tx and 10base-t modes, and can be controlled by software after reset. r educed m edia i ndependent i nterface (rmii) the interface in the BCM5228 is based on the low pin count (reduced) media independent interface (rmii) developed by the rmii consortium. a copy of the specification can be found on the consortium web site at:
BCM5228 data sheet 7/12/04 broadcom corporation page 6 mii management document 5228-ds09-405-r http://www.rmii-consort.com. the purpose of this interface is to provide a low-cost alternative to the ieee 802.3u[2] media independent interface (mii). the rmii is capable of supporting 10 megabit and 100 megabit data rates with a single clock, using independent 2-bit wide transmit and receive paths. a single 50-mhz synchronous reference clock is used as a timing reference for all transmitters and receivers. by doubling the clock frequency relative to the mii, four pins are saved in the data path, which uses two lines into each transmitter and two lines out of each receiver, compared to four lines used in each direction in the mii. since start-of-packet and end-of- packet timing information is preserved across the interface, the mac is able to derive the col signal from the receive and transmit data delimiters, saving another pin. transmit and receive clocks have been eliminated as well. all data transfers are synchronous with ref_clk. this poses less of a challenge for the transmitter than it does for the receiver, which is now required to buffer output data in a fifo un til an edge of the ref_clk is suitably aligned. the received data bits and the rx_dv signal are passed through the fifo, but the crs_dv bit is not. it is asserted for the time the wire is receiving a frame. if the remote transmitter is idle, and no data need be passed from the receiver, status information can be made available by setting bit 1 of register 10h. out-of- band signaling consists of 2 di-bit pairs immediately following the last di-bit pair of a received packet. the 2 di-bit pairs c onsist of full-duplex, link speed - msb, lsb and rxer, fifo error - msb, lsb. mii m anagement management of each transceiver within the BCM5228 remains the same as it was under the mii specification. each phy contains an independent set of mii management registers. they share a single mdc/mdio serial interface. each transceiver has a unique address and must be accessed individually. the common base address for the group of eight individual transceivers is defined by configuring the five external phyad address input pins. s erial m edia i ndependent i nterface (smii) the smii is an alternative to both the mii and rmii. the objective is to reduce the number of pins required to interconnect the mac and the phy. this is accomplished by clocking data and control signals in and out of each phy on a pair of pins at a rate of 125 mhz. the smii mode is selected by pulling the smii_en pin high during power-on reset. data and control signals passing from the mac to the phy use the serial transmit (stx) line. data and control signals passing from the phy to the mac use the serial receive (srx) line. all bit transfers are synchronous with clock (sclk) at 125 mhz. frame synchronization is provided by a fourth line (sync), asserted at the beginning of each frame, which occurs every 10 cycles of sclk. each phy is provided with an stx and an srx pair. pins txd0{x} and rxd0{x}, where x is the number of the specific phy, are used to perform the stx and srx functions. the BCM5228 chip has a single sclk and sync input that is common to all phys. pins ref_clk and ssync are used for these functions. receive data and control information are passed from the phy to the mac in 10 bit frames. in 100 mbps mode, each frame represents a new byte of data. in 10 mbps mode, each byte of data is repeated 10 times. the mac can sample any one of every 10 frames. since the timing of data coming from a remote transmitter is not synchronized with the local sclk or sync lines and can contain errors in frequency, a fifo capable of storing 28 bits is provided in each receive path. the received data bits and the rx_dv signal are passed through the fifo, but the crs bit is not. it is asserted for the time the wire is receiving a frame. if the remote transmitter is idle and no data need be passed from the receiver, status information becomes available.
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r interrupt mode page 7 transmit data and control information are passed from the mac to the phy in 10 bit frames, as in the receive path. in 100 mbps mode, each frame represents a new byte of data. in 10 mbps mode, each byte of data is repeated 10 times, and the phy can transmit any one of every 10 frames. i nterrupt m ode the BCM5228 can be programmed to provide an interrupt output consisting of an or of the eight interrupts, one from each phy. the interrupt feature is disabled by default. the interrupt capability is enabled by setting mii register 1ah, bit 14. the sled_do pin becomes the intr# pin, when the serial_en is pulled low during power-up reset. if a serial led mode is required, hardware interrupt can be obtained by wire oring led2{1:8} open drain outputs and programming led2 to output interrupt by setting txer/led1{5:3} pins to a 5 during power-on reset. the status of each interrupt source is also reflected in register 1ah, bits 1, 2 and 3. the sources of interrupt are change in link, speed or full-duplex status. if any type of inte rrupt occurs, the interrupt status bit, register 1ah, bit 0 is set. in addition, each transceiver has its own register controlling the interrupt function. if the interrupt enable bit is set to 0, no status bits sets, and no interrupts are generated. if the interrupt enable bit is s et to 1, the following conditions apply: if mask status bits are to 0 and the interrupt mask is set to 1, status bits are set but no interrupts are generated. if mask status bits are set to 0 and the interrupt mask is set to 0, status bits and interrupts are available. if mask status bits are set to 1 and the interrupt mask is set to 0, no status bits and no interrupts are available. changes from active to inactive or vice versa causes an interrupt. setting register 1ah, bit 8 high masks all interrupts, regardless of the settings of the individual mask bits.
BCM5228 data sheet 7/12/04 broadcom corporation page 8 interrupt mode document 5228-ds09-405-r
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r hardware signal definition table page 9 section 2: hardware signal definition table these conventions are used in the following table: # = active low i = digital input o = digital output i/o = bidirectional i a = analog input o a = analog output i pu = digital input with internal pull-up i pd = digital input with internal pull-down o od = open-drain output o 3s = tri-state output i/o pd = bidirectional with internal pull-down b = bias bus naming convention: pin label followed by {port #} pin type table 2: pin definitions BCM5228b BCM5228f BCM5228u pin label i/o description media connections a12,b12 a11,b11 a08,b08 a07,b07 t06,r06 t07,r07 t10,r10 t11,r11 166,167 178,177 184,185 196,195 64,65 76,75 82,83 94,93 165,166 173,172 179,180 198,197 62,63 81,80 87,88 95,94 rd+{1}, rd?{1} rd+{2}, rd?{2} rd+{3}, rd?{3} rd+{4}, rd?{4} rd+{5}, rd?{5} rd+{6}, rd?{6} rd+{7}, rd?{7} rd+{8}, rd?{8} i a receive pair. differential data from the media is received on the rd signal pair. a13,b13 a10,b10 a09,b09 a06,b06 t05,r05 t08,r08 t09,r09 t12,r12 164,165 180,179 182,183 198,197 62,63 78,77 80,81 96,95 163,164 175,174 177,178 200,199 60,61 83,82 85,86 97,96 td+{1}, td?{1} td+{2}, td?{2} td+{3}, td?{3} td+{4}, td?{4} td+{5}, td?{5} td+{6}, td?{6} td+{7}, td?{7} td+{8}, td?{8} o a transmit pair. differential data is transmitted to the media on the td signal pair.
BCM5228 data sheet 7/12/04 broadcom corporation page 10 hardware signal definition table document 5228-ds09-405-r d12,e12 d11,e11 d08,e08 e07,d07 n09,m09 n10,m10 n11,m11 n12,m12 171,170 173,174 189,188 191,192 69,68 71,72 87,86 89,90 sd+{1}, sd?{1} sd+{2}, sd?{2} sd+{3}, sd?{3} sd+{4}, sd?{4} sd+{5}, sd?{5} sd+{6}, sd?{6} sd+{7}, sd?{7} sd+{8}, sd?{8} i pd 100base-fx signal detect. indicates signal quality status on the fiber-optic link in 100base-fx mode. when the signal quality is good, the sd+ pin should be driven high relative to the sd ? pin. 100base-fx mode is disabled when both pins are simultaneously pulled low or left unconnected. reduced media independent interface (rmii) t15 99 100 ref_clk i reference clock input. this pin must be driven with a continuous 50-mhz clock in the rmii application and a 125-mhz clock in the smii application. it provides timing for crs_dv, rxd1, rxd0, tx_en, txd1,txd0, and rx_er. accuracy shall be 50 ppm, with a duty cycle between 35% and 65% inclusive. c03 b02 b01 a01 t01 r01 p04 p03 4 3 208 207 53 52 51 50 4 3 208 207 53 52 51 50 tx_en{1:8} i pd transmit enable. in rmii mode,active high indicates that the mac is presenting di-bits on txd1,txd0 for transmission. tx_en is asserted synchronously with the first nibble of the preamble and remains asserted while all di-bits to be transmitted are presented to the rmii. tx_en transitions synchronously with respect to ref_clk. d16 e16 f15 f16 g15 g16 h15 h16 j15 j16 k15 k16 l15 l16 m15 m16 149 150 145 146 139 140 135 136 127 128 123 124 117 118 113 114 149 150 145 146 139 140 135 136 127 128 123 124 117 118 113 114 txd1{1} txd0{1} txd1{2} txd0{2} txd1{3} txd0{3} txd1{4} txd0{4} txd1{5} txd0{5} txd1{6} txd0{6} txd1{7} txd0{7} txd1{8} txd0{8} i pd transmit data input. in rmii mode, txd1,txd0 dibit wide data is input on these pins for transmission by the phy. the data is synchronous with ref_clk. txd1 is the most significant bit. values other than 00 on txd1,txd0 while tx_en is deasserted are ignored by the phy. in smii mode, the txd0{1:8} form the stxd pins for each phy. table 2: pin definitions (cont.) BCM5228b BCM5228f BCM5228u pin label i/o description
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r hardware signal definition table page 11 a02 a03 b04 a04 r03 r02 t03 t02 204 203 202 201 59 58 57 56 206 205 204 203 57 56 55 54 crs_dv{1:8} o 3s carrier sense/receive data valid. in rmii mode, crs_dv shall be asserted by the phy when the medium is non-idle. the data on rxd1,rxd0 is considered valid once crs_dv is asserted. during a false carrier event, crs_dv shall remain asserted for the duration of carrier activity. crs_dv is not synchronized with respect to ref_clk. d14 d15 e14 e15 f12 f13 g12 g14 h12 h13 j12 j14 k12 k13 l12 l14 151 152 147 148 141 142 137 138 129 130 125 126 119 120 115 116 151 152 147 148 141 142 137 138 129 130 125 126 119 120 115 116 rxd1{1} rxd0{1} rxd1{2} rxd0{2} rxd1{3} rxd0{3} rxd1{4} rxd0{4} rxd1{5} rxd0{5} rxd1{6} rxd0{6} rxd1{7} rxd0{7} rxd1{8} rxd0{8} o 3s receive data outputs. in rmii mode, rxd1,rxd0 data is output synchronous with ref_clk. for each clock period in which crs_dv is asserted, rxd1,rxd0 transfers 2 bits of data from the phy. rxd1 is the most significant bit. in smii mode, the rxd0{1:8} form the srxd pins for each phy. d02 d01 c02 c01 n03 m01 m02 l01 8 7 6 5 43 42 41 40 8 7 6 5 43 42 41 40 rx_er{1:8} o 3s receive error detected. in rmii mode, rx_er is asserted high for one or more ref_clk periods to indicate that an error was detected somewhere in the frame presently being transferred from the phy. rx_er transitions synchronously with respect to ref_clk. serial media independent interface (smii) h01 23 23 smii_en/sled_clk i/o pu smii enable. active high. an active high or being left unconnected during power-on reset selects the smii mode, while an active low selects the rmii mode. serial led clock. after power-on reset, if serial or low-cost serial led mode is enabled, this pin sources the clock for serial data sled_do. for details, see ?led modes? on page 29 . table 2: pin definitions (cont.) BCM5228b BCM5228f BCM5228u pin label i/o description
BCM5228 data sheet 7/12/04 broadcom corporation page 12 hardware signal definition table document 5228-ds09-405-r p15 105 105 ssync i pd smii sync. in smii mode, this pin must be connected to a free running sync pulse occurring 1 of every 10 clock cycles. in rmii mode, this pin is nc (no connect). data and controls are transferred through txd0 and rxd0 between respective mac and phy in default smii mode. if source synchronous enable, ssmii_en, is high, then ssync provides sync for txd0 only and smii_rsync from the BCM5228 provides sync for rxd0. r15 103 103 ssmii_en i pd smii source synchronous (s3mii) enable. active high. when s3mii is enabled, the BCM5228 provides a source synchronous receive clock (smii_rxc) and a sync (smii_rsync) for mac to use. the BCM5228 uses smii_txc along with ssync to receive data from the mac. signals crs_dv, txer, txen, and rxer are not used when source synchronous mode is enabled. r16 106 106 smii_rxc o 3s smii source synchronous receive clock. optional 125-mhz clock in smii mode for mac use to clock in rxd0. p16 107 107 smii_rsync o 3s smii source synchronous sync. in s3mii mode, this pin provides a source synchronous sync pulse for mac to use for rxd0 if source synchronous is enabled. t16 104 104 smii_txc i pd smii source synchronous transmit clock. 125-mhz clock in smii mode for BCM5228 to clock in txd0 if source synchronous is enabled. management data i/o j01 32 32 mdio i/o pu management data i/o. this serial input/ output bit is used to read from and write to the rmii registers. the data value on the mdio pin is valid and latched on the rising edge of mdc. k01 31 31 mdc i pd management data clock. the mdc clock input must be provided to allow rmii management functions. clock frequencies up to 25 mhz are supported. g05 h05 h04 j05 j03 24 25 26 27 28 24 25 26 27 28 phyad{4:0} i pd phy address selects. these inputs set the base address for mii management phy addresses. also serve as test control inputs along with testen to select the nand-chain test mode. table 2: pin definitions (cont.) BCM5228b BCM5228f BCM5228u pin label i/o description
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r hardware signal definition table page 13 h02 22 22 masterphy/ sframe i/o pd master phy address mode. active high. this forces phy address 0 to be a global write address for all phys within the BCM5228. an active high during power-on reset selects the master phy address mode, while an active low or being left unconnected selects the normal address mode. serial led frame. after power-on reset, this pin sources the serial led frame output signal if serial led mode is enabled. mode c16 157 157 reset# i pu reset. active low. resets the BCM5228. pin not included in nand chain. n15 109 109 f100 i pu 10/100 mode select. when high and anen is low, all transceivers are forced to 100base-x operation. when low and anen is low, all transceivers are forced to 10base-t operation. when anen is high, f100 has no effect on the operation. m13 108 108 anen i pu auto-negotiation enable. active high. when pulled high, auto-negotiation begins immediately after reset. when low, auto- negotiation is disabled after reset. auto- negotiation can be enabled under software control (register 0, bit 12) if auto-negotiation is enabled through hardware. c15 156 156 fdxen i pd full-duplex mode enable. the fdxen pin is logically ored with an mii control bit to generate an internal full-duplex enable signal. when fdxen is high, the BCM5228 can operate in full-duplex mode as determined by auto-negotiation. when fdxen is low, the internal control bit (register 0, bit 8) determines the full-duplex operating mode. initial value of the internal control bit is zero. g01 19 19 txer_en i/o pu txer enable. active high. when pulled high during power-on reset, txer[1:8]/led1[1:8] pins become txer[1:8] input. otherwise they become led1[1:8] output. f05 20 20 mdix_dis i/o pd hp auto-mdix disable. active high. when pulled high during reset, automatic tx cable swap detection function of the BCM5228 is disabled. leave this pin unconnected for normal operation. f04 17 17 testen i pd test enable. active high test control input used along with phyad[4:0] to select the nand-chain test mode. this test mode is latched when testen is pulsed high, then low, with phyad[4:0]=10111. this pin is not included in the nand chain and must be pulled low or left unconnected during normal operation. table 2: pin definitions (cont.) BCM5228b BCM5228f BCM5228u pin label i/o description
BCM5228 data sheet 7/12/04 broadcom corporation page 14 hardware signal definition table document 5228-ds09-405-r led g03 21 21 serial_en i/o pd serial led enable. active high. serial led mode is enabled if this pin is high and the lc- ser_en pin is low during power-on reset. serial led mode and low-cost serial led mode cannot be active at the same time. for details, see ?led modes? on page 29 . g02 18 18 lc_ser_en i/o pu low-cost serial led enable. active high. low-cost serial led mode is enabled if this pin is high and ser_en pin is high during power-on reset. low-cost serial led mode and serial led mode can not be active at the same time. for details, see ?led modes? on page 29 . k02 30 30 sled_do/intr# o od serial led data. active low serial led data. this pin becomes serial led data output if ser_en pin is high during power- on reset. for details, see ?led modes? on page 29 . phy interrupt. active low output. this pin becomes interrupt output if ser_en pin is low during power-on reset. f01 f02 e01 e02 p01 p02 n02 n01 12 11 10 9 47 46 45 44 12 11 10 9 47 46 45 44 tx_er{1:8} led1{1:8} i/o pd txer[1:8]. active high input. this pin becomes txer input if txer_en pin is high during power-on reset. txer function is typically used in hstr application for transmitting halt codes. txer[1:8] pins are sampled during power-on reset to set the default led output for led1, led2 and led3. for details, see ?led modes? on page 29 . led1[1:8]. active low output. this pin becomes led1 output if txer_en pin is low during power-on reset. led1 can be configured to output one of link, speed, activity, full-duplex, transmit, receive, interrupt or collision status. for details, see ?led modes? on page 29 . c04 e06 d05 c05 m07 n07 m06 n06 185 186 187 188 68 69 70 71 led2{1:8} o od led2. active low. this pin can be configured to output one of speed, activity, full- duplex, transmit, receive, interrupt, collision, or link status. for details, see ?led modes? on page 29 . table 2: pin definitions (cont.) BCM5228b BCM5228f BCM5228u pin label i/o description
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r hardware signal definition table page 15 d03 b03 e05 d04 m05 n04 n05 m04 189 190 191 192 72 73 74 75 led3{1:8} o 3s led3. active low. the function of this led signal can be configured to output one of activity, full-duplex, link or speed status. for details, see ?led modes? on page 29 . bias a15 161 160 rdac b dac bias resistor. adjusts the current level of each of the transmit dac?s. a resistor of 1.24-k ? 1% must be connected between the rdac pin and agnd. a14 162 161 vref b voltage reference. low-impedance bias pin driven by the internal band-gap voltage reference. this pin must be left unconnected during normal operation. jtag l02 37 37 tdi i pu test mode select. serial data input to the jtag tap controller. sampled on the rising edge of tck. if unused, it can be left unconnected. l03 35 35 tms i pu test data input. single control input to the jtag tap controller used to traverse the test- logic state machine. sampled on the rising edge of tck. if unused, it can be left unconnected. l05 36 36 tck i pu test clock. clock input used to synchronize the jtag tap control and data transfers. if unused, it can be left unconnected. k04 33 33 tdo o 3s test data output. serial data output from the jtag tap controller. updated on the falling edge of tck. actively driven both high and low when enabled, otherwise high impedance. k05 34 34 trst# i pu test reset. asynchronous active-low reset input to the jtag tap controller. must be held low during power-up to insure the tap controller initializes to the test-logic-reset state. can be pulled low continuously when jtag functions are not used. must be held low for normal operation. power t14 101 102 pllvddc 2.5-v, phase locked loop vdd core, dvdd r14 98 99 pllgnd phase locked loop gnd p14 100 101 pllvddp pll pad vdd . tie this to the same supply as ovdd. a16 160 159 biasvdd 2.5-v, bias vdd table 2: pin definitions (cont.) BCM5228b BCM5228f BCM5228u pin label i/o description
BCM5228 data sheet 7/12/04 broadcom corporation page 16 hardware signal definition table document 5228-ds09-405-r b16 163 162 biasgnd bias gnd a05 c07 c10 c13 p07 p11 t04 t13 67 73 85 91 169 175 187 193 65 78 90 92 168 170 182 195 avdd 2.5-v, analog vdd b05 b14 b15 c06 c08 c09 c11 c12 d09 d10 e09 p05 p06 p08 p09 p10 p12 p13 r04 r13 61 66 70 74 79 84 88 92 97 168 172 176 181 186 190 194 199 59 64 66 77 79 84 89 91 93 98 167 169 171 176 181 183 194 196 201 agnd analog gnd e04 e13 g04 k14 l04 n13 2 15 48 111 132 154 2 15 48 111 132 154 dvdd 2.5-v, digital core vdd c14 f03 g06 j13 m03 n14 1 14 49 110 133 155 1 14 49 110 133 155 dgnd digital core gnd table 2: pin definitions (cont.) BCM5228b BCM5228f BCM5228u pin label i/o description
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r hardware signal definition table page 17 d06 e03 f14 g13 h03 k03 l13 m14 n08 13 16 39 121 122 143 144 13 16 39 67 121 122 143 144 184 ovdd 3.3v, digital periphery (output buffer) vdd d13 f06 f07 h11 h14 j04 l06 l07 n16 38 60 112 131 134 153 200 38 58 76 112 131 134 153 193 202 ognd digital periphery (output buffer) gnd table 2: pin definitions (cont.) BCM5228b BCM5228f BCM5228u pin label i/o description
BCM5228 data sheet 7/12/04 broadcom corporation page 18 hardware signal definition table document 5228-ds09-405-r
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r pinout diagrams page 19 section 3: pinout diagrams the the pinout diagram for the BCM5228f (fx support) is illustrated on figure 2 . figure 2: BCM5228f pinout diagram the pinout diagram for the BCM5228u (utp support) is illustrated on figure 3 on page 20 . 186 184 183 185 187 1 10 11 34 33 35 36 37 38 39 40 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 6 7 8 9 3 4 5 2 120 111 110 87 88 86 85 84 83 82 81 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 115 114 113 112 118 117 116 119 160 151 150 127 128 126 125 124 123 122 121 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 155 154 153 152 158 157 156 159 41 50 51 74 73 75 76 77 78 79 80 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 46 47 48 49 43 44 45 42 182 173 172 161 162 163 164 165 166 167 168 169 170 171 177 176 175 174 180 179 178 181 208 199 198 188 189 190 191 192 193 194 195 196 197 203 202 201 200 206 205 204 207 dgnd txer{3} txer{2} tms trst# tck tdo mdio mdc sled_do nc phyad0 phyad1 phyad2 phyad3 phyad4 smii_en masterphy ser_en mdix_dis txer_en lc_ser_en testen ovdd dgnd ovdd txer{1} rxer{3} rxer{2} rxer{1} txer{4} txen{2} txen{1} rxer{4} dvdd dvdd ognd ovdd rxer{8} rxer{7} rxer{6} txen{7} txen{6} txer{5} dvdd dgnd txen{8} txer{8} txer{7} txer{6} rxer{5} tdi sd ? {6} sd+{6} agnd sd+{5} sd ? {5} avdd agnd rd ? {5} rd+{5} td ? {5} td+{5} agnd ognd crs_dv{5} crs_dv{6} crs_dv{7} crs_dv{8} nc nc txen{5} smii_rsync smii_rxc anen td ? {6} td + {6} agnd td + {7} td ? {7} ssync rd+{7} rd ? {7} agnd avdd sd ? {7} sd+{7} agnd sd+{8} pllgnd ref_clk avdd agnd rd ? {6} rd+{6} ssmii_en nc pllvddc pllvddp rd + {8} td ? {8} td + {8} agnd avdd agnd rd ? {8} sd ? {8} f100 txd0{6} txd1{6} rxd1{6} rxd0{6} txd1{5} txd0{5} rxd1{5} ovdd ovdd rxd0{7} rxd1{7} txd0{7} txd1{7} rxd0{8} rxd1{8} txd0{8} txd1{8} ognd dvdd rxd0{5} ognd dvdd dgnd ognd txd1{4} txd0{4} dgnd rxd1{4} rxd0{3} ovdd ovdd txd1{3} txd0{3} rxd1{3} rxd0{4} txd0{2} rxd1{2} rxd0{2} txd1{1} txd0{1} dgnd fdxen rxd0{1} ognd dvdd rxd1{1} txd1{2} rd + {4} avdd agnd biasgnd td + {1} vref rdac biasvdd nc nc reset# td ? {1} rd + {1} rd ? {1} agnd avdd sd ? {1} sd + {1} agnd sd + {2} sd ? {2} avdd agnd rd ? {2} rd + {2} td ? {2} td + {2} agnd td + {3} td ? {3} rd + {3} rd ? {3} sd + {4} agnd sd + {3} sd ? {3} agnd avdd sd ? {4} rd ? {4} td + {4} agnd ognd crs_dv{4} crs_dv{3} txen{4} txen{3} crs_dv{1} nc nc crs_dv{2} td ? {4} BCM5228 f (top view) smii_txc
BCM5228 data sheet 7/12/04 broadcom corporation page 20 pinout diagrams document 5228-ds09-405-r figure 3: BCM5228u pinout diagram 186 184 183 185 187 1 10 11 34 33 35 36 37 38 39 40 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 6 7 8 9 3 4 5 2 120 111 110 87 88 86 85 84 83 82 81 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 115 114 113 112 118 117 116 119 160 151 150 127 128 126 125 124 123 122 121 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 155 154 153 152 158 157 156 159 41 50 51 74 73 75 76 77 78 79 80 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 46 47 48 49 43 44 45 42 182 173 172 161 162 163 164 165 166 167 168 169 170 171 177 176 175 174 180 179 178 181 208 199 198 188 189 190 191 192 193 194 195 196 197 203 202 201 200 206 205 204 207 dgnd txer{3} txer{2} tms trst# tck tdo mdio mdc sled_do nc phyad0 phyad1 phyad2 phyad3 phyad4 smii_en masterphy ser_en mdix_dis txer_en lc_ser_en testen ovdd dgnd ovdd txer{1} rxer{3} rxer{2} rxer{1} txer{4} txen{2} txen{1} rxer{4} dvdd dvdd ognd ovdd rxer{8} rxer{7} rxer{6} txen{7} txen{6} txer{5} dvdd dgnd txen{8} txer{8} txer{7} txer{6} rxer{5} tdi led3#{5} led2#{8} led2#{7} led2#{6} led2#{5} ovdd agnd avdd agnd rd ? {5} rd+{5} td ? {5} td+{5} agnd ognd crs_dv{5} crs_dv{6} crs_dv{7} crs_dv{8} txen{5} smii_rsy nc smii_rxc anen agnd avdd agnd rd ? {6} rd + {6} ssync td ? {6} td + {6} agnd td + {7} td ? {7} rd + {7} rd ? {7} agnd agnd pllgnd led3#{6} led3#{7} led3#{8} ognd smii_txc ssmii_en pllvddc pllvddp ref_clk rd ? {8} rd + {8} td ? {8} td + {8} agnd avdd agnd avdd f100 txd0{6} txd1{6} rxd1{6} rxd0{6} txd1{5} txd0{5} rxd1{5} ovdd ovdd rxd0{7} rxd1{7} txd0{7} txd1{7} rxd0{8} rxd1{8} txd0{8} txd1{8} ognd dvdd rxd0{5} ognd dvdd dgnd ognd txd1{4} txd0{4} dgnd rxd1{4} rxd0{3} ovdd ovdd txd1{3} txd0{3} rxd1{3} rxd0{4} txd0{2} rxd1{2} rxd0{2} txd1{1} txd0{1} dgnd fdxen rxd0{1} ognd dvdd rxd1{1} txd1{2} agnd led2#{3} led2#{2} td + {1} td ? {1} biasgnd vref rdac biasvdd nc reset# rd + {1} rd ? {1} agnd avdd agnd avdd agnd rd ? {2} rd + {2} td ? {2} td + {2} agnd td + {3} td ? {3} rd + {3} rd ? {3} agnd avdd agnd ovdd led2#{1} led3#{3} led3#{2} led3#{1} led2#{4} agnd ognd led3#{4} avdd rd + {4} td ? {4} td + {4} agnd ognd txen{4} txen{3} crs_dv{3} crs_dv{2} crs_dv{1} crs_dv{4} rd ? {4} BCM5228u (top view)
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r pinout diagrams page 21 figure 4: bga pinout (top view) 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 a txen{4} crs_dv {1} crs_dv {2} crs_dv {4} a v dd td+{4} rd+{ 4} rd+{ 3} td+{3} td+{2} rd+{ 2} rd+{ 1} td+{ 1} v ref rda c bia sv dd a t b txen{3} txen{2} led3{2} crs_dv {3} a gnd td- {4} rd-{ 4} rd-{ 3} td-{ 3} td- {2} rd- {2} rd-{ 1} td-{ 1} a gnd a gnd bia sgnd b t c rxer{4}rxer{3}txen{1}led2{1}led2{4}agndavddagndagndavddagndagndavdddgndfdxenreset# c r d rxer{2} rxer{1} led3{1} led3{ 4} led2{ 3} ov dd sd-{ 4} sd+{ 3} a gnd a gnd sd+{ 2} sd+{ 1} ognd rxd1{1} rxd0{ 1} txd1{ 1} d r e tx_er{3}/ led1{3} tx_er{4}/ led1{4} ov dd dv dd led3{ 3} led2{ 2} sd+{ 4} sd-{ 3} a gnd nc sd- {2} sd-{ 1} dv dd rxd1{2} rxd0{ 2} txd0{ 1} e t f tx_er{1}/ led1{1} tx_er{2}/ led1{2} dgnd testen mdix_dis ognd ognd tgnd tgnd tgnd tgnd rxd1{3} rxd0{3} ov dd txd1{2} txd0{2} f t g txer_en lc_ser_ en serial_en dv dd phy a d4 dgnd tgnd tgnd tgnd tgnd tgnd rxd1{4} ov dd rxd0{4} txd1{ 3} txd0{ 3} g t h smii_en/ sled_cl k ma sterp hy / sframe ov dd phy a d2 phy a d3 tgnd tgnd tgnd tgnd tgnd ognd rxd1{5} rxd0{5} ognd txd1{4} txd0{4} h s j mdio nc phy a d0 ognd phy a d1 tgnd tgnd tgnd tgnd tgnd tgnd rxd1{6} dgnd rxd0{6} txd1{5} txd0{5} j m k mdc sled_do/ intr# ov dd tdo trst# tgnd tgnd tgnd tgnd tgnd tgnd rxd1{7} rxd0{7} dv dd txd1{ 6} txd0{ 6} k m l rxer{8} tdi tms dv dd tck ognd ognd tgnd tgnd tgnd tgnd rxd1{8} ov dd rxd0{8} txd1{7} txd0{7} l r m rxer{6} rxer{7} dgnd led3{8} led3{5} led2{7} led2{5} nc sd-{5} sd-{6} sd-{7} sd-{8} anen pllvddp txd1{8} txd0{8} m r n tx_er{8}/ led1{8} tx_er{7}/ led1{7} rxer{5} led3{ 6} led3{ 7} led2{ 8} led2{6} ov dd sd+{5} sd+{6} sd+{ 7} sd+{ 8} dv dd dgnd f100 ognd n t p tx_er{5}/ led1{5} tx_er{6}/ led1{6} txen{8} txen{7} agnd agnd avdd agnd agnd agnd avdd agnd agnd pllvddp ssync smii_ rsy nc p t r txen{6} crs_dv {6} crs_dv {5} a gnd td- {5} rd- {5} rd-{ 6} td-{ 6} td-{ 7} rd- {7} rd- {8} td- {8} a gnd pllgnd ssmii_en smii_ rxc r t t txen{5} crs_dv {8} crs_dv {7} a v dd td+{5} rd+{ 5} rd+{ 6} td+{ 6} td+{7} rd+{7} rd+{ 8} td+{ 8} a v dd pllv ddc ref_clk smii_ txc t t c 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 t r note: tgnd balls are thermal grounds r t
BCM5228 data sheet 7/12/04 broadcom corporation page 22 pinout diagrams document 5228-ds09-405-r table 3: bga ballout by signal name signal name ball signal name ball signal name ball agnd b05 crs_dv{5} r03 masterphy/sframe h02 agnd b14 crs_dv{6} r02 mdc k01 agnd b15 crs_dv{7} t03 mdio j01 agnd c06 crs_dv{8} t02 mdix_dis f05 agnd c08 dgnd c14 nc e10 agnd c09 dgnd f03 nc j02 agnd c11 dgnd g06 nc m08 agnd c12 dgnd j13 ognd d13 agnd d09 dgnd m03 ognd f06 agnd d10 dgnd n14 ognd f07 agnd e09 dvdd e04 ognd h11 agnd p05 dvdd e13 ognd h14 agnd p06 dvdd g04 ognd j04 agnd p08 dvdd k14 ognd l06 agnd p09 dvdd l04 ognd l07 agnd p10 dvdd n13 ognd n16 agnd p12 f100 n15 ovdd d06 agnd p13 fdxen c15 ovdd e03 agnd r04 lc_ser_en g02 ovdd f14 agnd r13 led2{1} c04 ovdd g13 anen m13 led2{2} e06 ovdd h03 avdd a05 led2{3} d05 ovdd k03 avdd c07 led2{4} c05 ovdd l13 avdd c10 led2{5} m07 ovdd m14 avdd c13 led2{6} n07 ovdd n08 avdd p07 led2{7} m06 pllvddp p14 avdd p11 led2{8} n06 phyad0 j03 avdd t04 led3{1} d03 phyad1 j05 avdd t13 led3{2} b03 phyad2 h04 biasgnd b16 led3{3} e05 phyad3 h05 biasvdd a16 led3{4} d04 phyad4 g05 crs_dv{1} a02 led3{5} m05 pllgnd r14 crs_dv{2} a03 led3{6} n04 pllvddc t14 crs_dv{3} b04 led3{7} n05 rd?{1} b12 crs_dv{4} a04 led3{8} m04 rd?{2} b11
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r pinout diagrams page 23 rd-{3} b08 rxer{4} c01 td?{7} r09 rd-{4} b07 rxer{5} n03 td?{8} r12 rd-{5} r06 rxer{6} m01 td+{1} a13 rd-{6} r07 rxer{7} m02 td+{2} a10 rd-{7} r10 rxer{8} l01 td+{3} a09 rd-{8} r11 sd-{1} e12 td+{4} a06 rd+{1} a12 sd-{2} e11 td+{5} t05 rd+{2} a11 sd-{3} e08 td+{6} t08 rd+{3} a08 sd-{4} d07 td+{7} t09 rd+{4} a07 sd-{5} m09 td+{8} t12 rd+{5} t06 sd-{6} m10 tdi l02 rd+{6} t07 sd-{7} m11 tdo k04 rd+{7} t10 sd-{8} m12 testen f04 rd+{8} t11 sd+{1} d12 tgnd f08 rdac a15 sd+{2} d11 tgnd f09 ref_clk t15 sd+{3} d08 tgnd f10 reset# c16 sd+{4} e07 tgnd f11 rxd0{1} d15 sd+{5} n09 tgnd g07 rxd0{2} e15 sd+{6} n10 tgnd g08 rxd0{3} f13 sd+{7} n11 tgnd g09 rxd0{4} g14 sd+{8} n12 tgnd g10 rxd0{5} h13 serial_en g03 tgnd g11 rxd0{6} j14 sled_do/intr# k02 tgnd h06 rxd0{7} k13 smii_rsync p16 tgnd h07 rxd0{8} l14 smii_rxc r16 tgnd h08 rxd1{1} d14 smii_txc t16 tgnd h09 rxd1{2} e14 smii_en/sled_clk h01 tgnd h10 rxd1{3} f12 ssmii_en r15 tgnd j06 rxd1{4} g12 ssync p15 tgnd j07 rxd1{5} h12 tck l05 tgnd j08 rxd1{6} j12 td-{1} b13 tgnd j09 rxd1{7} k12 td-{2} b10 tgnd j10 rxd1{8} l12 td-{3} b09 tgnd j11 rxer{1} d02 td-{4} b06 tgnd k06 rxer{2} d01 td-{5} r05 tgnd k07 rxer{3} c02 td-{6} r08 tgnd k08 table 3: bga ballout by signal name (cont.) signal name ball signal name ball signal name ball
BCM5228 data sheet 7/12/04 broadcom corporation page 24 pinout diagrams document 5228-ds09-405-r tgnd k09 txd0{7} l16 txen{6} r01 tgnd k10 txd0{8} m16 txen{7} p04 tgnd k11 txd1{1} d16 txen{8} p03 tgnd l08 txd1{2} f15 txer_en g01 tgnd l09 txd1{3} g15 tx_er{1}/led1{1} f01 tgnd l10 txd1{4} h15 tx_er{2}/led1{2} f02 tgnd l11 txd1{5} j15 tx_er{3}/led1{3} e01 tms l03 txd1{6} k15 tx_er{4}/led1{4} e02 trst# k05 txd1{7} l15 tx_er{5}/led1{5} p01 txd0{1} e16 txd1{8} m15 tx_er{6}/led1{6} p02 txd0{2} f16 txen{1} c03 tx_er{7}/led1{7} n02 txd0{3} g16 txen{2} b02 tx_er{8}/led1{8} n01 txd0{4} h16 txen{3} b01 vref a14 txd0{5} j16 txen{4} a01 txd0{6} k16 txen{5} t01 table 3: bga ballout by signal name (cont.) signal name ball signal name ball signal name ball
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r operational description page 25 section 4: operational description r esetting the BCM5228 there are two ways to reset each transceiver in the BCM5228. a hardware reset pin has been provided which resets all internal nodes inside the chip to a known state. the reset pulse must be asserted for at least 2 s. hardware reset should always be applied to a BCM5228 after power-up and after all clocks to the chip are running. each transceiver in the BCM5228 also has an individual software reset capability. to perform software reset, a 1 must be written to bit 15 of the mii control register 0 (see ?mii register map summary? on page 37 ) of the transceiver. this bit is self- clearing, meaning that a second write operation is not necessary to end the reset. there is no effect if a 0 is written to this bit. l oopback m ode the loopback mode allows in-circuit testing of the BCM5228 chip. all packets sent in through the txd pins are looped-back internally to the rxd pins, and are not sent out to the cable. incoming packets on the cable are ignored. the loopback mode can be entered by writing a 1 to bit 14 of the mii control register or by writing a 1 to bit 8 and bit 7 of shadow register 1dh. in order to resume normal operation the bits must be 0. several function bypass modes are also supported which can provide a number of different combinations of feedback paths during loopback testing. these bypass modes include: bypass scrambler, bypass mlt3 encoder and bypass 4b5b encoder. f ull -d uplex m ode the BCM5228 supports full-duplex operation. while in fu ll-duplex mode, a transceiver can simultaneously transmit and receive packets on the cable. by default, each transceiver in the BCM5228 powers up in half-duplex mode. when auto-negotiation is disabled, full-duplex operation can be enabled either by a pin (fdxen) or by an mii register bit (register 0 bit 8). when auto-negotiation is enabled in dte mode, full-duplex capability is advertised by default but can be overridden by a write to the auto-negotiation advertisement register (04h). 100base-fx m ode any of the BCM5228f transceivers can interface with an external 100base-fx fiber-optic driver and receiver instead of the magnetics module used with twisted-pair cable. the differential transmit and receive data pairs operate at pecl voltage levels instead of those required for twisted-pair transmission, if the termination scheme recommended in the application note
BCM5228 data sheet 7/12/04 broadcom corporation page 26 10base-t mode document 5228-ds09-405-r is used. the data is encoded using two-level nrzi instead of three-level mlt3. the data stream is not scrambled for fiber- optic transmission. the stream cipher function is bypassed when 100base-fx mode is selected. the external fiber-optic receiver detects signal status and communicate it to the BCM5228b or BCM5228f through the sd pins. in this mode, the internal signal detect function is bypassed. the 100base-fx mode is automatically selected whenever a valid differential signal is detected at the sd input pins. pulling both sd+ and sd? low simultaneously disables the 100base-fx mode. 10base-t m ode the same magnetics module is used to interface the twisted-pair cable in 10base-t mode and in 100base-tx mode. the data is two-level manchester coded instead of three-leve l mlt3 and no scrambling/descrambling or 4b5b coding is performed. data and clock rates are decreased by a factor of 10, with the rmii interface operating at 2.5 mhz. i solate m ode each transceiver in the BCM5228 can be isolated from the rmi i/smii/s3mii interface. when a transceiver is put into isolate mode, all rmii/smii/s3mii input pins (txd0, txd1, tx_en, tx_er, ssync, smii_txc) are ignored and all rmii/smii/ s3mii output pins (crs_dv, rx_er, rxd0, rxd1, smii_rsync, smii_rxc) are set at high impedance. mii management pins (mdc, mdio,) and analog td, rd pins operate normally. writing a 1 to bit 10 of the mii control register 0 puts the port into isolate mode. writing a 0 to the same bit removes it from isolate mode. upon resetting the chip or resetting the isolated port, the isolate mode is off. s uper i solate m ode when the chip is in super isolate mode, in addition to isolate mode actions, the chip also sets the analog td pins to high impedance. writing a 1 to bit 3 of the mii register 1eh puts t he port into super isolate mode. writing a 0 to the same bit removes it from super isolate mode. upon resetting the chip or resetting the isolated port, the super isolate mode is off. a uto p ower -d own m ode the BCM5228 supports a low power mode called auto power-down mode. auto power-down mode is enabled by setting bit 5 of shadow register 1bh. when in this mode, the BCM5228 automatically enters the low power mode if the energy from the link partner is lost. similarly, the next time energy is detected, the chip resumes full power mode. when the BCM5228 is in this low power mode, it wakes up after approximately 2.5 to 5.0 seconds, as determined by bit 4 of shadow register 1bh, and sends a link pulse while monitoring energy from the link partner. if energy is detected, the BCM5228 enters full power mode and establishes link with the link partner. otherwise, the wake-up mode continues for a duration of approximately 40?600 milliseconds, as determined by bits [3:0] of shadow register 1bh before going to low power mode. see table43onpage66 for details of various bits.
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r jumbo packet mode page 27 j umbo p acket m ode in 100base-x mode, the BCM5228 can support jumbo packet size. the size of the packet that can be handled reliably depends on the descrambler lock timer settings and the receive fifo size. by default, the BCM5228 provides an effective 10 bits of receive fifo to allow for extremely large packet sizes. these modes are enabled by setting appropriate bits in the mii registers. table 4 shows the number of effective fifo bits supported. when changing the receive fifo size, it is necessary to identify the receive packet size requirement and set the descrambler timer lock accordingly. the descrambler lock is controlled by the jumbo packet enable bit located in register 1hbh, bit 10. the packet size that can be reliably received is the lower number indicated by two settings: the jumbo packet enable bit and the two extended fifo enable bits. phy a ddress each transceiver in the BCM5228 has a unique phy address for mii management. the phy address is determined by the using the base address, which is input on the phyad[4:0] pins. the following shows the addressing of the eight phys. phy0 = phyad + 0, phy1 = phyad + 1,... phy7 = phyad + 7 every time an mii write or read operation is executed, the transceiver compares the phy address with its own phy address definition. the operation is executed only when the addresses match. table 4: receive fifo size select jumbo packet fifo enable reg 1bh bit 9 extended fifo enable reg 10h bit 2 number of effective fifo bits supported packet size (bytes b ) b. the packet size calculation is based on 50 ppm clock tolerance for local and link partner. 0 0 10 12 500 0 1 20 25 000 1 0 20 25 000 11 40 (20 a ) a. in this mode, the BCM5228 operation is guaranteed to only 20 bits of effective fifo depth, although under some circumstances, it could behave as if the fifo depth is 40 bits. 50 000/25 000 table 5: jumbo packet enable and descrambler lock timer jumbo packet enable reg 1bh bit 10 descrambler lock timer packet size 0 720 s 9050 1 5792 s 72 400
BCM5228 data sheet 7/12/04 broadcom corporation page 28 hp auto-mdix document 5228-ds09-405-r hp a uto -mdix during auto-negotiation and in various operating modes, one end of the link must be configured as an mdi (media independent interface) crossover so that each transceiver?s transmitter is connected to the other?s receiver. the BCM5228 contains the ability to perform hp auto-mdix crossover, thus eliminating the need for crossover cable or cross-wired (mdix) ports. during auto-negotiation and in various operating modes, the BCM5228 normally transmits on td and receives on rd. when connected via a straight-through cable to another device that does not have hp auto-mdix, the BCM5228 automatically switches its transmitter to rd and its receiver to td to communicate with that device. if the link partner also has hp auto-mdix, then a random algorithm determines which end performs the crossover function. the hp auto-mdix feature is implemented in accordance with the ieee 802.3ab specification. the hp auto-mdix crossover feature is a function of auto-negotiation. therefore, if the BCM5228 is configured not to perform auto-negotiation, hp auto- mdix crossover does not work, and a specific cable is required to ensure that each transceiver?s transmitter is connected to the other?s receiver. the hp auto-mdix feature is enabled in hardware by pulling the mdix_dis pin low during power-on reset. if enabled by hardware, this feature can be disabled by setting bit 11 of the mii register 1ch to 0.
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r led modes page 29 section 5: led modes d escription the BCM5228 offers a rich set of led display outputs through serial and parallel led modes. there are two serial led modes available, serial led mode and low-cost serial led mode. the serial led mode provides compatibility with few other broadcom phys. serial led modes are selected by hardware only during power-on reset. when any serial led mode is enabled global hardware interrupt feature is not available. ho wever, if interrupt and a serial or a low-cost serial led mode is desired simultaneously, then a parallel led can be programmed to provide on interrupt output per port and eight such interrupt can be ored to obtain a global interrupt. s erial led m ode the serial led mode is enabled only by having the ser_en pin high and the lc_ser_en pin low during power-on reset. if serial led mode is enabled, then the low-cost serial led mode and hardware global interrupt are disabled. in serial led mode, the BCM5228 sources a serial data stream, the associated clock, and a framing signal as follows: serial data stream, sled_do, which is an active low bit stream containing 48 bits per frame. serial data clock, sled_clk, is used to clock out sled_do on the falling edge of this clock. sled-do is valid on the rising edge of this clock. sled_clk is approximately 3.125 mhz in forced 100base-t and -fx modes, and 2.5 mhz in all other modes. framing pulse, sframe, which is a logic high pulse occurring once every 48 sled_do bit times. sframe goes high coincident with bit 0 of port 1. when the serial led mode is enabled by hardware, the led stream is selected for sled_do as shown in table 6 , depending on the values of bits 14 and 15 of mii register 1ah. the data stream contains bit 0 to bit 5 for port 1, bit 0 to bit 5 for port 2, ? and bit 0 to bit 5 for port 8. note?a global interrupt indicates an interrupt from any of the eight phys as if they were ored together. a port interrupt is provided on a per-phy basis. table 6: serial led mode bit framing reg 1ah serial bit 5 serial bit 4 serial bit 3 serial bit 2 serial bit 1 serial bit 0 bit 15 = 0 bit 14 = 0 fdx col speed100 link transmit receive bit 15 = 0 bit 14 = 1 fdx global interrupt speed100 link port interrupt activity bit 15 = 1 bit 14 = 0 fdx col speed100 link fdx activity bit 15 = 1 bit 14 = 1 fdx global interrupt speed100 link fdx activity
BCM5228 data sheet 7/12/04 broadcom corporation page 30 low-cost serial le d mode document 5228-ds09-405-r l ow -c ost s erial led m ode the low-cost serial led mode is enabled by pulling both lc_ser_en pin and ser_en pin high during power-on reset. when enabled, serial led data stream, sled_do, is shifted out on the falling edge of sled_clk. sled_do is valid on the rising edge of this clock. the data is shifted in such a manner that the update of leds using a simple shift register that drive the display leds do not cause noticeable flicker in normal operation. there are six banks, bank 1 through bank 6, associated with si x led outputs. each bank has its own mii register bits that select led a signal to output from that bank. the selected signal from each bank is shifted out on the led_do pin in the following order for a total of 48 led outputs: bank 1 for port 1 through port 8 bank 2 for port 1 through port 8,?, bank 6 for port 1 through 8 the low-cost serial led mode programmable banks are located in the mii shadow register 1ah of port 2 and port 3. for programming details, see table 7 , table 8 , table 9 , table 10 , table 11 , and table 12 . the default led outputs are speed, link, full-duplex, activity, speed, and link for bank 1 through bank 6, respectively. table 7: low-cost serial mode bank 1 led selection mii shadow register a 1ah, phy 3, bits [2:0] a. the mii shadow register is accessed by setting mii register 1fh bit 7 to 1. value led selection serial bank 1 select bits[2:0] 0 speed 1 activity 2 full-duplex 3transmit 4 receive 5 interrupt 6 collision 7link table 8: low-cost serial mode bank 2 led selection mii shadow register a 1ah, phy 3, bits [5:3] a. the mii shadow register is accessed by setting mii register 1fh bit 7 to 1. value led selection serial led bank 2 select bits[2:0] 0link 1 speed 2 activity 3 full-duplex 4transmit 5 receive 6 interrupt 7collision
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r low-cost serial led mode page 31 table 9: low-cost serial mode bank 3 led selection mii shadow register a 1ah, phy 3, bits [8:6] a. the mii shadow register is accessed by setting mii register 1fh bit 7 to 1. value led selection serial led bank 3 select bits[2:0] 0 full-duplex 1transmit 2 receive 3 interrupt 4collision 5link 6 speed 7 activity table 10: low-cost serial mode bank 4 led selection mii shadow register a 1ah, phy 2, bits [2:0] a. the mii shadow register is accessed by setting mii register 1fh bit 7 to 1. value led selection serial led bank 4 select bits[2:0] 0 activity 1 full-duplex 2transmit 3 receive 4 interrupt 5collision 6link 7 speed table 11: low-cost serial mode bank 5 led selection mii shadow register a 1ah, phy 2, bits [5:3] a. the mii shadow register is accessed by setting mii register 1fh bit 7 to 1. value led selection serial led bank 5 select bits[2:0] 0 speed 1 activity 2 full-duplex 3transmit 4 receive 5 interrupt 6collision 7link
BCM5228 data sheet 7/12/04 broadcom corporation page 32 low-cost serial le d mode document 5228-ds09-405-r table 12: low-cost serial mode bank 6 led selection mii shadow register a 1ah, phy 2, bits [8:6] a. the mii shadow register is accessed by setting mii register 1fh bit 7 to 1. value led selection serial bank 6 select bits[2:0] 0link 1 speed 2 activity 3 full-duplex 4transmit 5 receive 6 interrupt 7collision
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r parallel led mode page 33 p arallel led m ode the BCM5228u offers a parallel led mode that is active all the time. there are 3 led pins, led1, led2, and led3 for each port each of which can be individually configured to output one of many led signals. configuration can be accomplished either by hardware or programming mii register bits. led1 pins are shared with txer. these pins can be configured to output led1 if txer_en pin is pulled low during power-on reset. for unmanaged system design using the BCM5228u, the par allel led pins for each port can be programmed through hardware during power-on reset by pull-down or pull-up combinations of txer/led1 [1:8] pins. pull-up and pull-down of these pins should be done using a series 4.7-k ? resistor to ovdd or ognd respectively and led drive and polarity should be such that the active low output on led1 lights up the led. led2 and led3 can be configured to output one of link, speed, activity, full-duplex, transmit, receive, interrupt or collision while led3 can be configured to be one of activity, full-duplex, link or speed. software configuration of led1, led2 and led3 is accomplished through mii shadow register 1ah, phy 1, bits [7:0]. for details, see table 13 , table 14 , and table 15 . because led2{1:8} pins are open drain, they can be wire 0red together and configured (by hardware during power-on reset or through software by setting bits in the mii shadow register) to provide global hardware interrupt when required. table 13: parallel led mode led1 selection txer[3:1] mii shadow register a 1ah, phy 1, bits [2:0] a. the mii shadow register is accessed by setting mii register 1fh bit 7 to 1. value led1 selection power-on led1 select bits[2:0] led1 select[2:0] 0link 1 speed 2 activity 3 full-duplex 4transmit 5 receive 6 interrupt 7collision table 14: parallel led mode led2 selection txer [6:4] mii shadow register a 1ah, phy 1, bits [5:3] a. the mii shadow register is accessed by setting mii register 1fh bit 7 to 1. value led2 selection power-on reset led2 select[2:0] led2 select[2:0] 0 speed 1 activity 2 full-duplex 3transmit 4 receive 5 interrupt 6 collision 7link
BCM5228 data sheet 7/12/04 broadcom corporation page 34 parallel led mode document 5228-ds09-405-r table 15: parallel led mode led3 selection txer [8:7] mii shadow register a 1ah, phy 1, bits [7:6] a. the mii shadow register is accessed by setting mii register 1fh bit 7 to 1. value led3 selection power-on reset led3 select[1:0] led3 select[1:0] 0 activity 1 full-duplex 2link 3 speed
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r register summary page 35 section 6: register summary mii m anagement i nterface : r egister p rogramming the BCM5228 fully complies with the ieee 802.3u media independent interface (mii) specification. the mii management interface registers of each port are serially written-to and read from using a common set of mdio and mdc pins. a single clock waveform must be provided to the BCM5228 at a rate of 0?25 mhz through the mdc pin. the serial data is communicated on the mdio pin. every mdio bit must have the same period as the mdc clock. the mdio bits are latched on the rising edge of the mdc clock. every mii read or write instruction frame contains the following fields: preamble (pre). thirty-two consecutive 1 bits must be sent through the mdio pin to the BCM5228 to signal the beginning of an rmii instruction. fewer than thirty-two 1 bits causes the remainder of the instruction to be ignored. start of frame (st). a 01 pattern indicates that the start of the instruction follows. operation code (op). a read instruction is indicated by 10, while a write instruction is indicated by 01. phy address (phyad). a 5-bit phy address follows next, with the msb transmitted first. the phy address allows a single mdio bus to access multiple phy chips. the BCM5228 supports a complete address space with phyad[4:0] input-pins used as the base address for selecting one of the eight transceivers. register address (regad). a 5-bit register address follows, with the msb transmitted first. the register map of the BCM5228, containing register addresses and bit definitions, are provided on the following pages. turnaround (ta). the next two bit times are used to avoid contention on the mdio pin when a read operation is performed. for a write operation, 10 must be sent to the BCM5228 chip during these two bit times. for a read operation, the mdio pin must be placed into high-impedance during these two bit times. the chip drives the mdio pin to 0 during the second bit time. data . the last 16 bits of the frame are the actual data bits. for a write operation, these bits are sent to the BCM5228, whereas, for a read operation, these bits are driven by the BCM5228. in either case, the msb is transmitted first. when writing to the BCM5228, the data field bits must be stable 10 ns before the rising edge of mdc, and must be held valid for 10 ns after the rising edge of mdc. when reading from the BCM5228, the data field bits are valid after the rising-edge of mdc until the next rising edge of mdc. idle . a high impedance state of the mdio line. all tri-state drivers are disabled and the phy?s pull-up resistor pulls the mdio line to logic 1. table 16: mii management frame format operation pre st op phyad regad ta data idle direction read 1 ... 1 01 10 aaaaa rrrrr zz z0 z ... z d ... d z z driven to BCM5228 driven by BCM5228 write 1 ... 1 01 01 aaaaa rrrrr 10 d ... d z driven to BCM5228
BCM5228 data sheet 7/12/04 broadcom corporation page 36 mii management interface: regi ster programming document 5228-ds09-405-r at least one or more idle states ar e required between frames. the following s hows two examples of mii write and read instructions. to put a transceiver with phy address 00001 into loopback mode, the following mii write instruction must be issued: 1111 1111 1111 1111 1111 1111 1111 1111 0101 00001 00000 10 0100 0000 0000 0000 1... to determine if a phy is in the link pass state, the following mii read instruction must be issued: 1111 1111 1111 1111 1111 1111 1111 1111 0110 00001 00001 zz zzzz zzzz zzzz zzzz 1... for the mii read operation, the BCM5228 drives the mdio line during the ta and data fields (the last 17 bit times). a final 65th clock pulse must be sent to close the transaction and cause a write operation to take place.
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r mii management interf ace: register programming page 37 mii r egister m ap s ummary table 17 contains the mii register map summary for each port of the BCM5228. the register addresses are specified in hex form, and the name of register bits have been abbreviated. when writing to any register, preserve existing values of the reserved bits by completing a ?read/modify write.? ignore reserved bits when reading registers. never write to an undefined register. the reset values of the registers are shown in the init column. some o f these values could be different depending on how the device is configured and also depending on the device revision value. table 17: mii register map summary addr name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 init 00h control soft reset loopback force100 auto-neg enable power down isolate restart auto-neg full-duplex collision test reserved 3000h 01h status t4 capable tx fdx capable tx capable base-t fdx capable 10base-t capable reserved mf pream suppress auto-neg comp remote fault auto-neg capable link status jabber detect extd reg capable 7809h 02hphyid high0 0 0 00000 0 1 0 0 00 0 0 0040h 03h phyid low 0 1 1 0 0 0 01 1 model # 101 revision # 0 0 0 0 61d0h 04h aut-neg advertise next page reserved remote fault reserved tech pause adv t4 adv tx fdx adv tx adv base-t fdx adv base-t advertised selector field[4:0] 0 0 0 0 1 01e1h 05h link partner ability lp next page lp acknowledge lp rem fault reserved tech lp pause lp t4 lp tx fdx lp tx lp base-t fdx lp base-t link partner selector field [4:0] 0000h 06h auto-neg expansion reserved par det fault lp next pg able next pg able page recvd lp auto- neg able 0004h 07h next page next page reserved message page acknowledge2 toggle message/unformatted code field 2001h 08h lp next page next page reserved message page acknowledge2 toggle message/unformatted code field 0000h 10h 100base-x aux control reserved trans disable reserved bypass 4b5b enc/dec bypass scram/ descram bypass nrzi enc/dec bypass rcv sym align baseline wander disable fef enable reserved extended fifo enable reserved 0000h 11h 100base-x aux status reserved r/smii over under run fx mode locked current 100 link status current remote fault reserved false carrier detected bad esd detected rcv error detected xmt error detected lock error detected mlt3 error detected 0000h 12h 100base-x rcv error counter receive error counter[15:0] 0000h 13h 100base-x false carrier counter rmii/smii overrun/underrun counter[7:0] f alse carrier sense counter[7:0] 0000h 14h 100base-x disconnect counter rmii/smii fastrxd rmii/smii slowrxd reserved 0200h 15h reserved reserved 0300h 16h reserved reserved 0000h 17h ptest reserved 0000h 18h auxiliary control/ status jabber disable force link reserved txdac power mode hsq lsq edge rate[1:0] auto-neg enable indication force 100 indication sp100 indication fdx indication 003xh 19h auxiliary status summary auto-neg complete auto-neg complete ack auto-neg ack detect auto-neg ability detect auto-neg pause auto-neg hcd auto-neg pardet fault lp remote fault lp page rcvd lp auto-neg able sp100 indication link status internal auto-neg enabled full-duplex indication 0000h
BCM5228 data sheet 7/12/04 broadcom corporation page 38 mii management interface: register programming document 5228-ds09-405-r 1ah interrupt fdx led enable intr enable reserved fdx mask spd mask link mask intr mask reserved global interrupt status fdx change spd change link change intr status 0f0xh 1bh auxiliary mode2 reserved 10base-t dribble correct jumbo packet enable jumbo packet fifo enable reserved block 10base-t echo mode traffic meter led mode activity led force on serial led enable (phy 2 of 8) sqe disable activity/ link led enable qual parallel detect mode reserved 008ah 1ch 10base-t auxiliary error and general status reserved mdix status mdix manual swap hp auto- mdix disable manchstr code err (base-t) eof err (base-t) reserved 0 0 1 reserved auto-neg enable indicator force 100 indicator sp100 indicator fdx indicator 002xh 1dh auxiliary mode reserved reserved activity led force inactive link led force inactive reserved block txen mode reserved x000h 1eh auxiliary multi-phy hcd tx fdx hc t4 hcd tx hcd 10base-t fdx hcd 10base-t reserved restart auto-neg auto-neg complete reserved ack detect ability detect super isolate reserved rxer code mode 0000h 1fh broadcom test reserved shadow register enable reserved 000bh table 18: mii shadow register map summary (mii register 1fh, bit7 = 1) addr name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 init 18h reserved reserved 003ah 1ah auxiliary mode 4 (phy 1) reserved mii led select enable parallel led3 select[1:0] parallel led2 select[2:0] parallel led1 select[2:0] 3000h 1ah auxiliary mode 4 (phy 2) reserved serial bank 6 select[2:0] serial bank 5 select[2:0] serial bank 4 select[2:0] 3000h 1ah auxiliary mode 4 (phy 3) reserved serial bank 3 select[2:0] serial bank 2 select[2:0] serial bank 1 select[2:0] 3000h 1bh auxiliary status 2 mlt3 detect cable length 100x[2:0] adc peak amplitude[5:0] apd enable apd sleep timer apd wake-up timer[3:0] 0001h 1ch auxiliary status 3 noise[7:0] (root mean square error) flp detect nlp detect link break timer expire link fail timer expire fifo consumption[3:0] 0000h 1dh auxiliary mode 3 reserved fifo size select[3:0] 0004h 1eh auxiliary status4 packet length counter[15:0] 0000h table 17: mii register map summary (cont.) addr name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 init
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r mii management interface: register programming page 39 mii c ontrol r egister soft reset . to reset the BCM5228 by software control, a 1 must be written to bit 15 of the control register using an mii write operation. the bit clears itself after the reset process is complete, and need not be cleared using a second mii write. writes to other control register bits have no effect until the re set process is completed, which requires approximately 1 microsecond. writing a 0 to this bit has no effect. since this bit is self-clearing, after a few cycles from a write operation, it returns a 0 when read. loopback . the BCM5228 can be placed into loopback mode by writing a 1 to bit 14 of the control register. the loopback mode can be cleared by writing a 0 to bit 14 of the control register, or by resetting the chip. when this bit is read, it retur ns a 1 when the chip is in software-controlled loopback mode, otherwise it returns a 0. forced speed selection . if auto-negotiation is enabled, this bit has no effect on the speed selection. however, if auto- negotiation is disabled by software control, the operating speed of the BCM5228 can be forced by writing the appropriate value to bit 13 of the control register. writing a 1 to this bit forces 100base-x operation, while writing a 0 forces 10base- t operation. when this bit is read, it returns the value of the software-controlled forced speed selection only. in order to re ad the overall state of forced speed selection, including both har dware and software control, use bit 2of the auxiliary error and general status register, 1ch. auto-negotiation enable . auto-negotiation can be disabled by one of two methods: hardware or software control. if the anen input pin is driven to a logic 0, auto-negotiation is disabled by hardware control. if bit 12 of the control register is written with a value of 0, auto-negotiation is disabled by software control. when auto-negotiation is disabled in this manner, writing a 1 to the same bit of the control register or resetting the chip re-enables auto-negotiation. writing to this bit has no table 19: mii control register (address 00d, 00h) bit name r/w description default 15 soft reset r/w (sc) 1 = phy reset 0 = normal operation 0 14 loopback r/w 1 = loopback mode 0 = normal operation 0 13 forced speed selection r/w 1 = 100 mbps 0 = 10 mbps 1 12 auto-negotiation enable r/w 1 = auto-negotiation enable 0 = auto-negotiation disable 1 11 power down ro 0 = normal operation 0 10 isolate r/w 1 = electrically isolate phy from rmii 0 = normal operation 0 9 restart auto-negotiation r/w (sc) 1 = restart auto-negotiation process 0 = normal operation 0 8 duplex mode r/w 1 = full-duplex 0 = half-duplex 0 7 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ?? 0 6:0 reserved a ?? 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation.
BCM5228 data sheet 7/12/04 broadcom corporation page 40 mii management interface: regi ster programming document 5228-ds09-405-r effect when auto-negotiation has been disabled by hardware control. when read, this bit returns the value most recently written to this location, or 1 if it has not been written since the last chip reset. power down . the BCM5228 does not implement power-down mode. however, the device does support auto power-down mode (see ?auto power-down mode? on page 26 ). isolate. each individual phy can be isolated from its media independent interface by writing a 1 to bit 10 of the control register. all rmii outputs is tri-stated and all rmii/smii/s3mii inputs are ignored. because the mii/smii/s3mii management interface is still active, the isolate mode can be cleared by writing a 0 to bit 10 of the control register, or by resetting th e chip. when this bit is read, it returns a 1 when the chip is in isolate mode, otherwise, it returns a 0. see also ?isolate mode? on page 26 . restart auto-negotiation . bit 9 of the control register is a self-clearing bit that allows the auto-negotiation process to be restarted, regardless of the current status of the auto-negotiation state machine. in order for this bit to have an effect, auto-negotiation must be enabled. writing a 1 to this bit restarts the auto-negotiation, while writing a 0 to this bit has no effect. since the bit is self-clearing after only a few cycles, it always returns a 0 when read. the operation of this bit is identical to bit 9 of the auxiliary multiple phy register. duplex mode. by default, the BCM5228 powers up in half-duplex mode. the chip can be forced into full-duplex mode by writing a 1 to bit 8 of the control register while auto-negotiation is disabled. half-duplex mode can be resumed by writing a 0 to bit 8 of the control register, or by resetting the chip.
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r mii status register page 41 mii s tatus r egister 100base-t4 capability. the BCM5228 is not capable of 100base-t4 operation, and returns a 0 when bit 15 of the status register is read. 100base-x full-duplex capability. the BCM5228 is capable of 100base-x full-duplex operation, and returns a 1 when bit 14 of the status register is read. 100base-x half-duplex capability. the BCM5228 is capable of 100base-x half-duplex operation, and returns a 1 when bit 13 of the status register is read. 10base-t full-duplex capability. the BCM5228 is capable of 10base-t full-duplex operation, and returns a 1 when bit 12 of the status register is read. 10base-t half-duplex capability. the BCM5228 is capable of 10base-t half-duplex operation, and returns a 1 when bit 11 of the status register is read. mf preamble suppression. this bit is the only writable bit in the status register. setting this bit to a 1 allows subsequent mii management frames to be accepted with or without t he standard preamble pattern. when preamble suppression is enabled, only two preamble bits are required between successive management commands, instead of the normal 32. table 20: mii status register (address 01d, 01h) bit name r/w description default 15 100base-t4 capability ro 0 = not 100base-t4 capable 0 14 100base-tx fdx capability ro 1 = 100base-tx full-duplex capable 1 13 100base-tx capability ro 1 = 100base-tx half-duplex capable 1 12 10base-t fdx capability ro 1 = 10base-t full-duplex capable 1 11 10base-t capability ro 1 = 10base-t half-duplex capable 1 10:7 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ? ? 0000 6 mf preamble suppression r/w 1 = preamble may be suppressed 0 = preamble always required 0 5 auto-negotiation complete ro 1 = auto-negotiation process completed 0 = auto-negotiation process not completed 0 4 remote fault ro lh 1 = far-end fault condition detected 0 = no far-end fault condition detected 0 3 auto-negotiation capability ro 1 = auto-negotiation capable 0 = not auto-negotiation capable 1 2link status ro ll 1 = link is up (link pass state) 0 = link is down (link fail state) 0 1 jabber detect ro lh 1 = jabber condition detected 0 = no jabber condition detected 0 0 extended capability ro 1 = extended register capable 1 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation.
BCM5228 data sheet 7/12/04 broadcom corporation page 42 phy identifier registers document 5228-ds09-405-r auto-negotiation complete . bit 5 of the status register returns a 1 if the auto-negotiation process has been completed and the contents of registers 4, 5 and 6 are valid. remote fault. the phy returns a 1 in bit 4 of the status register when its link partner has signalled a far-end fault condition. when a far-end fault occurs, the bit is latched at 1 and remains so until the register is read and the remote fault condition has been cleared. this only applies to the fx mode of operation. auto-negotiation capability . the BCM5228 is capable of performing ieee auto-negotiation, and returns a 1 when bit 4 of the status register is read, regardless of whether or not the auto-negotiation function has been disabled. link status. the BCM5228 returns a 1 on bit 2 of the status register when the link state machine is in link pass, indicating that a valid link has been established. otherwise, it returns 0. when a link failure occurs after the link pass state has been entered, the link status bit is latched at 0 and remains so until the bit is read. after the bit is read, it becomes 1 if the l ink pass state has been entered again. jabber detect. 10base-t operation only. the BCM5228 returns a 1 on bit 1 of the status register if a jabber condition has been detected. after the bit is read, or if the chip is reset, it reverts to 0. extended capability. the BCM5228 supports extended capability registers, and returns a 1 when bit 0 of the status register is read. several extended registers have been implemented in the BCM5228, and their bit functions are defined later in this section. phy i dentifier r egisters broadcom corporation has been issued an organizationally unique identifier (oui) by the ieee. it is a 24-bit number, 00-10-18, expressed as hex values (the two most significant bits (oui[23:22]) of the oui are not represented). that number, along with the broadcom model number for the BCM5228 part, 1ch, and broadcom revision number, 00h, is placed into two mii registers. the translation from oui, model number and revision number to phy identifier register occurs as follows: phyid high[15:0] = oui[21:6] phyid low[15:0] = oui[5:0] + model[5:0] + rev[3:0] figure 21 on page 42 shows the result of concatenating these values to form the mii identifier registers phyid high and phyid low. table 21: phy identifier registers (addresses 02d and 03d, 02h and 03h) bit name r/w description value 15:0 mii address 00010 ro phyid high 0040h 15:0 mii address 00011 ro phyid low xxxxh
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r auto-negotiation advertisement register page 43 a uto -n egotiation a dvertisement r egister next page. the BCM5228 supports the next page function. remote fault. writing a 1 to bit 13 of the advertisement register causes a remote fault indicator to be sent to the link partner during auto-negotiation. writing a 0 to this bit or resetting the chip clears the remote fault transmission bit. this bit retur ns the value last written to it, or else 0, if no write has been completed since the last chip reset. reserved technologies . ignore output when read. pause . pause operation for full-duplex links. the use of this bit is independent of the negotiated data rate, medium, or link technology. the setting of this bit indicates the availability of additional dte capability when full-duplex operation is in us e. this bit is used by one mac to communicate pause capability to its link partner and has no effect on phy operation. advertise. bits 9:5 of the advertisement register allow the user to customize the ability information transmitted to the link partner. the default value for each bit reflects the abilities of the BCM5228. by writing a 1 to any of the bits, the correspon ding ability is transmitted to the link partner. writing a 0 to any bit causes the corresponding ability to be suppressed from transmission. resetting the chip restores the default bit values. reading the register returns the values last written to the corresponding bits, or else the default values if no write has been completed since the last chip reset. advertise selector field. bits 4:0 of the advertisement register contain the value 00001, indicating that the chip belongs to the 802.3 class of phy transceivers. table 22: auto-negotiation advertisement register (address 04d, 04h) bit name r/w description default 15 next page r/w 1 = next page ability is enabled 0 = next page ability is disabled 0 14 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ?? 0 13 remote fault r/w 1 = transmit remote fault 0 12:11 reserved technologies ro ignore when read 00 10 pause r/w 1 = pause operation for full-duplex 0 9 advertise 100base-t4 r/w 1 = advertise t4 capability 0 = do not advertise t4 capability 0 8 advertise 100base-x fdx r/w 1 = advertise 100base-x full-duplex 0 = do not advertise 100base-x full-duplex 1 7 advertise 100base-x r/w 1 = advertise 100base-x 1 6 advertise 10base-t fdx r/w 1 = advertise 10base-t full-duplex 0 = do not advertise 10base-t full-duplex 1 5 advertise 10base-t r/w 1 = advertise 10base-t 1 4:0 advertise selector field r/w indicates 802.3 00001 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation.
BCM5228 data sheet 7/12/04 broadcom corporation page 44 auto-negotiation link partner (lp) ability register document 5228-ds09-405-r a uto -n egotiation l ink p artner (lp) a bility r egister the values contained in the auto-negotiation link partner ability register are only guaranteed to be valid after auto- negotiation has successfully completed, as indicated by bit 5 of the mii status register. lp next page. bit 15 of the link partner ability register returns a value of 1 when the link partner implements the next page function and has next page information that it wants to transmit. the BCM5228 does not implement the next page function, and thus ignores the next page bit, except to copy it to this register. lp acknowledge. bit 14 of the link partner ability register is used by auto-negotiation to indicate that a device has successfully received its link partner?s link code word. lp remote fault. bit 13 of the link partner ability register returns a value of 1 when the link partner signals that a remote fault has occurred. the BCM5228 simply copies the value to this register and does not act upon it. reserved technologies . ignore when read. lp advertise pause . indicates that the link partner pause bit is set. lp advertise. bits 9:5 of the link partner ability register reflect the abilities of the link partner. a 1 on any of these bits indicates that the link partner is capable of performing the corresponding mode of operation. bits 9:5 are cleared any time auto-negotiation is restarted or the BCM5228 is reset. link partner selector field. bits 4:0 of the link partner ability register reflect the value of the link partner?s selector field. these bits are cleared any time auto-negotiation is restarted or the chip is reset. table 23: auto-negotiation link partner ability register (address 05d, 05h) bit name r/w description default 15 lp next page ro link partner next page bit 0 14 lp acknowledge ro link partner acknowledge bit 0 13 lp remote fault ro link partner remote fault indicator 0 12:11 reserved technologies ro ignore when read 000 10 lp advertise pause ro link partner has pause capability 0 9 lp advertise 100base-t4 ro link partner has 100base-t4 capability 0 8 lp advertise 100base-x fdx ro link partner has 100base-x fdx capability 0 7 lp advertise 100base-x ro link partner has 100base-x capability 0 6 lp advertise 10base-t fdx ro link partner has 10base-t fdx capability 0 5 lp advertise 10base-t ro link partner has 10base-t capability 0 4:0 link partner selector field ro link partner selector field 00000 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation.
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r auto-negotiation expansion register page 45 a uto -n egotiation e xpansion r egister parallel detection fault. bit 4 of the auto-negotiation expansion register is a read-only bit that gets latched high when a parallel detection fault occurs in the auto-negotiation state machine. for further details, consult the ieee standard. the bit is reset to 0 after the register is read or when the chip is reset. link partner next page able. bit 3 of the auto-negotiation expansion register returns a 1 when the link partner has next page capabilities. it has the same value as bit 15 of the link partner ability register. next page able. the BCM5228 returns 1 when bit 2 of the auto-negotiation expansion register is read indicating that it has next page capabilities. page received. bit 1 of the auto-negotiation expansion register is latched high when a new link code word is received from the link partner, checked, and acknowledged. it remains high until the register is read, or until the chip is reset. link partner auto-negotiation able . bit 0 of the auto-negotiation expansion register returns a 1 when the link partner is known to have auto-negotiation capability. before any auto-negotiation information is exchanged, or if the link partner does not comply with ieee auto-negotiation, the bit returns a value of 0. table 24: auto-negotiation expansion register (address 06d, 06h) bit name r/w description default 15:5 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ? ? 000h 4 parallel detection fault ro lh 1 = parallel detection fault. 0 = no parallel detection fault 0 3 link partner next page able ro 1 = link partner has next page capability 0 = link partner does not have next page 0 2 next page able ro 1 = next page able 1 1 page received ro 1 = new page has been received 0 = new page has not been received 0 0 link partner auto-negotiation able ro lh 1 = link partner has auto-negotiation capability 0 = link partner does not have auto-negotiation 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation.
BCM5228 data sheet 7/12/04 broadcom corporation page 46 auto-negotiation next page register document 5228-ds09-405-r a uto -n egotiation n ext p age r egister next page. indicates whether this is the last next page to be transmitted. message page. differentiates a message page from an unformatted page. acknowledge 2. indicates that a device has the ability to comply with the message. toggle. used by the arbitration function to ensure synchronization with the link partner during next page exchange. message code field. an 11-bit wide field, encoding 2048 possible messages. unformatted code field. an 11-bit wide field, which can contain an arbitrary value. table 25: next page transmit register (address 07d, 07h) bit name r/w description default 15 next page r/w 1 = additional next page(s) follows 0 = last page 0 14 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ? ?0 13 message page r/w 1 = message page 0 = unformatted page 1 12 acknowledge 2 r/w 1 = complies with message 0 = cannot comply with message 0 11 toggle ro 1 = previous value of the transmitted link code word equalled logic zero 0 = previous value of the transmitted link code word equalled logic one 0 10: 0 message/unformatted code field r/w 1 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation.
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r auto-negotiation link partner (lp) next page transmit register page 47 a uto -n egotiation l ink p artner (lp) n ext p age t ransmit r egister next page. indicates whether this is the last next page. message page. differentiates a message page from an unformatted page. acknowledge 2. indicates that link partner has the ability to comply with the message. toggle. used by the arbitration function to ensure synchronization with the link partner during next page exchange. message code field. an 11-bit wide field, encoding 2048 possible messages. unformatted code field. an 11-bit wide field, which can contain an arbitrary value. table 26: next page transmit register (address 08d, 08h) bit name r/w description default 15 next page ro 1 = additional next page(s) follows 0 = last page 0 14 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ? ?0 13 message page ro 1= message page 0 = unformatted page 0 12 acknowledge 2 ro 1 = complies with message 0 = cannot comply with message 0 11 toggle ro 1 = previous value of the transmitted link code word equalled logic zero 0 = previous value of the transmitted link code word equalled logic one 0 10:0 message/unformatted code field ro 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation.
BCM5228 data sheet 7/12/04 broadcom corporation page 48 100base-x auxiliary control register document 5228-ds09-405-r 100base-x a uxiliary c ontrol r egister transmit disable. the transmitter can be disabled by writing a 1 to bit 13 of mii register 10h. the transmitter output (td) is forced into a high impedance state. bypass 4b5b encoder/decoder. the 4b5b encoder and decoder can be bypassed by writing a 1 to bit 10 of mii register 10h. the transmitter sends 5b codes from the txer and txd1,txd0 pins directly to the scrambler. txen must be active, and frame encapsulation (insertion of j/k and t/r codes) is not performed. the receiver places descrambled and aligned 5b codes onto the rxer, rxd1 and rxd0 pins. crs is asserted when a valid frame is received. bypass scrambler/descrambler. the stream cipher function can be disabled by writing a 1 to bit 9 of mii register 10h. the stream cipher function can be re-enabled by writing a 0 to this bit. bypass nrzi encoder/decoder. the nrzi encoder and decoder can be bypassed by writing a 1 to bit 8 of mii register 10h, causing 3-level nrzi data to be transmitted and received on the cable. normal operation (3-level nrzi encoding and decoding) can be re-enabled by writing a 0 to this bit. table 27: 100-base-x auxiliary control register (address 16d, 10h) bit name r/w description default 15:14 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ? ? 0 13 transmit disable r/w 1 = transmitter disabled in phy 0 = normal operation 0 12:11 reserved a ? ? 0 10 bypass 4b5b encoder/decoder r/w 1 = transmit and receive 5b codes over rmii pins 0 = normal rmii 0 9 bypass scrambler/descrambler r/w 1 = scrambler and descrambler disabled 0 = scrambler and descrambler enabled 0 8 bypass nrzi encoder/decoder r/w 1 = nrzi encoder and decoder is disabled 0 = nrzi encoder and decoder is enabled 0 7 bypass receive symbol alignment r/w 1 = 5b receive symbols not aligned 0 = receive symbols aligned to 5b boundaries 0 6 baseline wander correction disable r/w 1 = baseline wander correction disabled 0 = baseline wander correction enabled 0 5 fef enable r/w 1 = far-end fault enabled 0 = far-end fault disabled 0 4:3 reserved a ? ? 0 2 extended fifo enable r/w 1 = extended fifo mode 0 = normal fifo mode 0 1:0 reserved a ? ? 00 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation.
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r 100base-x auxiliary status register page 49 bypass receive symbol alignment. receive symbol alignment can be bypassed by writing a 1 to bit 7 of mii register 10h. when used in conjunction with the bypass 4b5b encoder/decoder bit, unaligned 5b codes are placed directly on the rxer and rxd1, rxd0 pins. baseline wander correction disable. the baseline wander correction circuit can be disabled by writing a 1 to bit 6 of mii register 10h. the BCM5228 corrects for baseline wander on the receive data signal when this bit is cleared. fef enable. controls the far-end fault mechanism associated with 100base-fx operation. a 1 enables the fef function, and a 0 disables it. extended fifo enable. controls the extended receive fifo mechanism. this bit may have to be set if the jumbo packet enable bit is set. see table 4 on page 27 for details. 100base-x a uxiliary s tatus r egister table 28: 100base-x auxiliary status register (address 17d, 11h) bit name r/w description default 15:12 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ? ?0 11 r/smii overrun/underrun detected ro 1 = error detected 0 = no error 0 10 fx mode ro 1 = 100base-fx mode 0 = 100base-tx or 10base-t mode pin 9locked ro 1 = descrambler locked 0 = descrambler unlocked 0 8 current 100base-x link status ro 1 = link pass 0 = link fail 0 7 remote fault ro 1 = remote fault detected 0 = no remote fault detected 0 6 reserved a ?? 0 5 false carrier detected ro lh 1 = false carrier detected since last read 0 = no false carrier since last read 0 4 bad esd detected ro lh 1 = esd error detected since last read 0 = no esd error since last read 0 3 receive error detected ro lh 1 = receive error detected since last read 0 = no receive error since last read 0 2 transmit error detected ro lh 1 = transmit error code received since last read 0 = no transmit error code received since last read 0 1 lock error detected ro lh 1 = lock error detected since last read 0 = no lock error since last read 0 0 mlt3 code error detected ro lh 1 = mlt3 code error detected since last read 0 = no mlt3 code error since last read 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation.
BCM5228 data sheet 7/12/04 broadcom corporation page 50 100base-x receive error counter document 5228-ds09-405-r r/smii overrun/underrun detected. the phy returns a 1 in bit 11, when the rmii receive fifo encounters an overrun or underrun condition. fx mode. returns a value derived from the sd input pins. returns a 1 when sd are driven with a valid differential signal level. returns a 0 when both sd+ and sd? are simultaneously driven low. locked . the phy returns a 1 in bit 9 when the descrambler is locked to the incoming data stream. otherwise, it returns a 0. current 100base-x link status . the phy returns a 1 in bit 8 when the 100base-x link status is good. otherwise, it returns a 0. remote fault. the phy returns a 1 while its link partner is signalling a far-end fault condition. otherwise, it returns a 0. false carrier detected. the phy returns a 1 in bit 5 of the extended status register if a false carrier has been detected since the last time this register was read. otherwise, it returns a 0. bad esd detected. the phy returns a 1 in bit 4 if an end-of-stream delimiter error has been detected since the last time this register was read. otherwise, it returns a 0. receive error detected. the phy returns a 1 in bit 3 if a packet was received with an invalid code since the last time this register was read. otherwise, it returns a 0. transmit error detected. the phy returns a 1 in bit 2 if a packet was received with a transmit error code since the last time this register was read. otherwise, it returns a 0. lock error detected. the phy returns a 1 in bit 1 if the descrambler has lost lock since the last time this register was read. otherwise, it returns a 0. mlt3 code error detected. the phy returns a 1 in bit 0 if an mlt3 coding error has been detected in the receive data stream since the last time this register was read. otherwise it returns a 0. 100base-x r eceive e rror c ounter receive error counter [15:0] . this counter increments each time the BCM5228 receives a non-collision packet containing at least one receive error. the counter automatically clears itself when read. when the counter reaches its maximum value, ffh, it stops counting receive errors until cleared table 29: 100base-x receive er ror counter (address 18d, 12h) bit name r/w description default 15:0 receive error counter [15:0] r/w number of non-collision packets with receive errors since last read 0000h
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r 100base-x fals e carrier sense counter page 51 100base-x f alse c arrier s ense c ounter rmii/smii overrun/underrun counter [7:0] . the rmii/smii overrun/underrun counter increments each time the BCM5228 detects an overrun or underrun of the rmii/smii fifos. the counter automatically clears itself when read. when the counter reaches its maximum value, ffh, it stops counting overrun/underrun errors until cleared. false carrier sense counter [7:0] . this counter increments each time the BCM5228 detects a false carrier on the receive input. this counter automatically clears itself when read. when the counter reaches its maximum value (ffh), it stops counting false carrier sense errors until it is cleared. 100base-x d isconnect c ounter rmii/smii fast rxd. extended fifo operation only. bit 15 of the disconnect counter register indicates the fifo state machine has detected fast receive data relative to the ref_clk input. rmii/smii slow rxd. extended fifo operation only. bit 14 of the disconnect counter register indicates the fifo state machine has detected slow receive data relative to the ref_clk input. table 30: 100base-x false carrier sense counter (address 19d, 13h) bit name r/w description default 15:8 rmii/smii overrun/underrun counter [7:0] r/w number of rmii overruns/underruns since last read 00h 7:0 false carrier sense counter [7:0] r/w number of false carrier sense events since last read 00h table 31: 100base-x disconnect counter bit name r/w description default 15 rmii/smii fast rxd r/o 1 = in extended fifo mode, detect fast receive data 0 = normal 0 14 rmii/smii slow rxd r/o 0 = normal 1 = in extended fifo mode, detect slow receive data 0 13:8 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ? ? 000010 7:0 reserved a ?? 00h note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation.
BCM5228 data sheet 7/12/04 broadcom corporation page 52 auxiliary control/status register document 5228-ds09-405-r a uxiliary c ontrol /s tatus r egister jabber disable. 10base-t operation only. bit 15 of the auxiliary control register allows the user to disable the jabber detect function, defined in the ieee standard. this function shuts off the transmitter when a transmission request has exceeded a maximum time limit. by writing a 1 to bit 15 of the auxiliary control register, the jabber detect function is disabled. writing a 0 to this bit or resetting the chip restores normal operation. reading this bit returns the value of jabber detect disable. link disable. writing a 1 to bit 14 of the auxiliary control register allows the user to disable the link integrity state machines, and place the BCM5228 into forced link pass status. writing a 0 to this bit or resetting the chip restores the link integrity functions. reading this bit returns the value of link integrity disable. hsq:lsq . extend or decrease the squelch levels for detection of incoming 10base-t data packets. the default squelch levels implemented are those defined in the ieee standard. the high-squelch and low-squelch levels are useful for situations where the ieee-prescribed levels are inadequate. the squelch levels are used by the crs/link block to filter out noise and recognize only valid packet preambles and link integrity pulses. extending the squelch levels allows the BCM5228 to operate properly over longer cable lengths. decreasing the squelch levels can be useful in situations where there is a high level of noise present on the cables. reading these 2 bits returns the value of the squelch levels. table 32: auxiliary control/status register (address 24d, 18h) bit name r/w description default 15 jabber disable r/w 1= jabber function disabled in phy 0 = jabber function enabled in phy 0 14 link disable r/w 1= link integrity test disabled in phy 0 = link integrity test is enabled in phy 0 13:8 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ? ? 000000 7:6 hsq:lsq r/w these two bits define the squelch mode of the 10base-t carrier sense mechanism: 00 = normal squelch 01 = low squelch 10 = high squelch 11 = not allowed 00 5:4 edge rate [1:0] r/w 00 = 1 ns 01 = 2 ns 10 = 3 ns 11 = 4 ns 11 3 auto-negotiation indicator ro 1 = auto-negotiation activated 0 = speed forced manually 1 2 force 100/10 indication ro 1 = speed forced to 100base-x 0 = speed forced to 10base-t 1 1 speed indication ro 1 = 100base-x 0 = 10base-t 0 0 full-duplex indication ro 1 = full-duplex active 0 = full-duplex not active 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation.
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r auxiliary control/status register page 53 edge rate [1:0]. control bits used to program the transmit dac output edge rate in 100base-tx mode. these bits are logically anded with the er [1:0] input pins to produce the internal edge-rate controls (edge_rate [1] and er [1], edge_rate [0] and er [0]). auto-negotiation indicator . a read-only bit that indicates whether auto-negotiation has been enabled or disabled on the BCM5228. a combination of a 1 in bit 12 of the control register and a logic 1 on the anen input pin is required to enable auto-negotiation. when auto-negotiation is disabled, bit 3 of the auxiliary control register returns a 0. at all other times, i t returns a 1. force100/10 indication. a read-only bit that returns a value of 0 when one of following two cases is true: the anen pin is low and the f100 pin is low, or bit 12 of the control register has been written 0 and bit 13 of the control register has been written 0. when bit 8 of the auxiliary control register is 0, the speed of the chip is 10base-t. in all other cases, either the speed is not forced (auto-negotiation is enabled), or the speed is forced to 100base-x. speed indication. bit 1 of the auxiliary control register is a read-only bit that shows the true current operation speed of the BCM5228. a 1 bit indicates 100base-x operation, while a 0 indicates 10base-t. while the auto-negotiation exchange is performed, the BCM5228 is always operating at 10base-t speed full-duplex indication. bit 0 of the auxiliary control register is a read-only bit that returns a 1 when the BCM5228 is in full- duplex mode. in all other modes, it returns a 0.
BCM5228 data sheet 7/12/04 broadcom corporation page 54 auxiliary status summary register document 5228-ds09-405-r a uxiliary s tatus s ummary r egister this register contains copies of redundant status bits found elsewhere within the mii register space. descriptions for each of these individual bits can be found associated with their primary register descriptions. table 33: auxiliary status summary register (address 25d, 19h) bit name r/w description default 15 auto-negotiation complete ro 1 = auto-negotiation process completed 0 14 auto-negotiation complete acknowledge ro lh 1 = auto-negotiation completed acknowledge state 0 13 auto-negotiation acknowledge detected ro lh 1 = auto-negotiation acknowledge detected 0 12 auto-negotiation ability detect ro lh 1 = auto-negotiation for link partner ability 0 11 auto-negotiation pause ro BCM5228 and link partner pause operation bit set 0 10:8 auto-negotiation hcd ro 000 = no highest common denominator 001 = 10base-t 010 = 10base-t full-duplex 011 = 100base-tx 100 = 100base-t4 101 = 100base-tx full-duplex 11x = undefined 000 7 auto-negotiation parallel detection fault ro lh 1 = parallel detection fault 0 6 link partner remote fault ro 1 = link partner has signalled a far-end fault condition in fx mode 0 5 link partner page received ro lh 1 = new page has been received 0 4 link partner auto- negotiation able ro 1 = link partner is auto-negotiation capable 0 3 speed indicator ro 1 = 100 mbps 0 = 10 mbps 0 2link status ro ll 1 = link is up (link pass state) 0 1 auto-negotiation enabled ro 1 = auto-negotiation enabled 1 0 full-duplex indication ro ll 1 = full-duplex active 0 = full-duplex not active 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation.
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r interrupt register page 55 i nterrupt r egister fdx led enable. setting this bit enables the fdx led status to output serial led data in serial led mode. see table 6 on page 29 for details. intr enable. setting this bit enables interrupt mode. the state of this bit also affects which status signals are shifted out on the serial led data in serial led mode. see table 6 on page 29 for details. fdx mask. when this bit is set, changes in duplex mode do not generate an interrupt. spd mask. when this bit is set, changes in operating speed do not generate an interrupt. link mask. when this bit is set, changes in link status do not generate an interrupt. intr mask. master interrupt mask. when this bit is set, no interrupts are generated regardless of the state of the other mask bits. global interrupt indicator . a 1 indicates an interrupt is present within the BCM5228. fdx change. a 1 indicates a change of duplex status since last register read. a register read clears the bit. spd change. a 1 indicates a change of speed status since last register read. a register read clears the bit. link change. a 1 indicates a change of link status since last register read. a register read clears the bit. table 34: interrupt register (address 26d, 1ah) bit name r/w description default 15 fdx led enable r/w fdx led enable in serial led stream 0 14 intr enable r/w interrupt enable 0 13:12 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ? ?00 11 fdx mask r/w full-duplex interrupt mask 1 10 spd mask r/w speed interrupt mask 1 9 link mask r/w link interrupt mask 1 8 intr mask r/w master interrupt mask 1 7:5 reserved a ? ?000 4 global interrupt indicator ro 1= indicates an interrupt is present within the BCM5228 0 3 fdx change ro, lh duplex change interrupt 0 2 spd change ro, lh speed change interrupt 0 1 link change ro, lh link change interrupt 0 0 intr status ro, lh interrupt status 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation.
BCM5228 data sheet 7/12/04 broadcom corporation page 56 auxiliary mode 2 register document 5228-ds09-405-r intr status. represents status of the intr# pin. a 1 indicates that the interrupt mask is off and that one or more of the change bits are set. a register read clears the bit. a uxiliary m ode 2 r egister 10base-t dribble bit correct. when enabled, the phy rounds-down to the nearest nibble when dribble bits are present on the 10base-t input stream. jumbo packet enable. when enabled, the 100base-x unlock timer changes to allow long packets. see table 5 on page 27 for details. jumbo packet fifo enable . when enabled, the rmii/smii/s3mii receive fifo doubles from 7 nibbles to 14 nibbles. the jumbo packet fifo enable bit should be set to a 1 when jumbo packet mode is enabled. see table 4 on page 27 and table 5 on page 27 for details. table 35: auxiliary mode 2 register (address 27d, 1bh) bit name r/w description default 15:12 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ?? 0 11 10base-t dribble bit correct r/w 1 = enable 0 = disable 0 10 jumbo packet enable r/w 1 = enable 0 = disable 0 9 jumbo packet fifo enable r/w 1 = enable 0 = disable 0 8 reserved a ?? 0 7 block 10base-t echo mode r/w 1 = enable 0 = disable 1 6 traffic meter led mode r/w 1 = enable 0 = disable 0 5 activity led force on r/w 1 = on 0 = normal operation 0 4 reserved a ?? 1 3 reserved a ?? 1 2 activity/link led mode r/w 1 = enable 0 = disable 0 1 qual parallel detect mode r/w 1 = enable 0 = disable 1 0 reserved a ?? 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation.
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r 10base-t auxiliary error and general status register page 57 block 10base-t echo mode . when enabled, during 10base-t half-duplex tran smit operation, the txen signal does not echo onto the rxdv pin. the txen echoes onto the crs pin, and the crs deassertion directly follows the txen deassertion. traffic meter led mode. when enabled, the activity leds (actled# and fdxled# if full-duplex led and interrupt led modes are not enabled) do not blink based on the internal led clock (approximately 80 s of time). instead, they blink based on the rate of receive and transmit activity. each time a receive or transmit operation occurs, the led turns on for a minimum of 5 s. during light traffic, the led blinks at a low rate, while during heavier traffic the leds remain on. activity led force on . when set to 1, the col led, transmit led, receive led, and activity led are turned on. this bit has a higher priority than the activity led force inactive, bit 4, register 1dh. activity/link led mode . when enabled, the receive output goes active upon acquiring link and pulses during receive or transmit activity. qual parallel detect mode . this bit allows the auto-negotiation/parallel detection process to be qualified with information in the advertisement register. if this bit is not set, the local BCM5228 device is enabled to auto-negotiate, and the far-end device is a 10base-t or 100base-x non auto-negotiating legacy type, the local device auto-negotiates/parallel-detects the far-end device, regardless of the contents of its advertisement register (04h). if this bit is set, the local device compares the link speed detected to the contents of its advertisement register. if the particular link speed is enabled in the advertisement register, the local device asserts link. if the link speed is disabled in this register, then the local device does not assert link and continues monitoring for a matching capability link speed. 10base-t a uxiliary e rror and g eneral s tatus r egister table 36: 10base-t auxiliary error and general status register (address 28d, 1ch) bit name r/w description default 15:14 reserved a ?? 0 13 mdix status ro 0 = mdi is in use 1 = mdix is in use 0 12 mdix manual swap r/w 0 = mdi or mdix if mdix is not disabled 1 = force mdix 0 11 hp auto-mdix disable r/w 0 = enable hp auto-mdix 1 = disable hp auto-mdix 0 10 manchester code error ro 1 = manchester code error (10base-t) 0 9 end-of-frame error ro 1 = eof detection error (10base-t) 0 8 reserved a ?? 0 7:5 reserved a ?? 001 4 reserved a ?? 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation.
BCM5228 data sheet 7/12/04 broadcom corporation page 58 10base-t auxiliary error and general status register document 5228-ds09-405-r all error bits in the auxiliary error and general status register are read-only and are latched high. when certain types of errors occur in the BCM5228, one or more corresponding error bits become 1. they remain so until the register is read, or until a chip reset occurs. all such errors necessarily result in data errors, and are indicated by a high value on the rxer output pin at the time the error occurs. mdix status. this bit, when read as a 1, indicates that the mdi td and rd signals for the BCM5228 have been swapped. the cause for this is one of the following: the mdix swap bit was manually set to a 1, or the hp auto-mdix function is enabled and the BCM5228 has detected an mdi cross-over cable. mdix manual swap. when this bit is set to a 1, the mdi td and rd signals for the BCM5228 are forced into being swapped. hp auto-mdix disable . when this bit is set to a 1, the hp auto-mdix function is disabled in the BCM5228. manchester code error. indicates that a manchester code violation was received. this bit is only valid during 10base-t operation. end-of-frame error. indicates that the end-of-frame (eof) sequence was improperly received, or not received at all. this error bit is only valid during 10base-t operation. auto-negotiation indication . a read-only bit that indicates whether auto-negotiation has been enabled or disabled on the BCM5228. a combination of a 1 in bit 12 of the control register and a logic 1 on the anen input pin is required to enable auto-negotiation. when auto-negotiation is disabled, bit 15 of the auxiliary mode register returns a 0. at all other times, it returns a 1. force 100/10 indication. a read-only bit that returns a value of 0 when one of following two cases is true: the anen pin is low and the f100 pin is low, or bit 12 of the control register has been written 0 and bit 13 of the control register has been written 0. when bit 2 of the auxiliary control register is 0, the speed of the chip is 10base-t. in all other cases, either the speed is not forced (auto-negotiation is enabled), or the speed is forced to 100base-x. speed indication. a read-only bit that shows the true current operation speed of the BCM5228. a 1 bit indicates 100base- x operation, while a 0 indicates 10base-t. while the auto-negotiation exchange is performed, the BCM5228 is always operating at 10base-t speed. 3 auto-negotiation indication ro 1 = auto-negotiation activated 0 = speed forced manually 1 2 force 100/10 indication ro 1 = speed forced to 100base-x 0 = speed forced to 10base-t 1 1 speed indication ro 1 = 100base-x 0 = 10base-t 0 0 full-duplex indication ro 1 = full-duplex active 0 = full-duplex not active 0 a. preserve existing values of reserved bi ts by completing a ?read/modify write.? table 36: 10base-t auxiliary error and general status register (address 28d, 1ch) note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation.
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r 10base-t auxiliary error and general status register page 59 full-duplex indication . a read-only bit that returns a 1 when the BCM5228 is in full-duplex mode. in all other modes, it returns a 0.
BCM5228 data sheet 7/12/04 broadcom corporation page 60 auxiliary mode register document 5228-ds09-405-r a uxiliary m ode r egister activity led force inactive. when set to 1, disables the col led, transmit led, receive led, and activity led. this bit has a lower priority than the activity led force on, bit 5 of register 1bh. link led disable . when set to 1, disables the link led output pin. when 0, link led output is enabled. block txen mode . when this mode is enabled, short ipgs of 1, 2, 3, or 4 txc cycles all result in the insertion of two idles before the beginning of the next packet?s jk symbols. table 37: auxiliary mode register (address 29d, 1dh) bit name r/w description default 15:5 reserved a a. preserve existing values of reserved bits by completing a read/modify write. ? ?000h 4 activity led force inactive r/w 1 = disable col led, transmit led, receive led, and activity led 0 = enable above leds 0 3 link led disable r/w 1 = disable link led output 0 = enable link led output 0 2 reserved a ? ?0 1block txen mode r/w 1 = enable block txen mode 0 = disable block txen mode 0 0 reserved a ? ?0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation.
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r auxiliary multiple phy register page 61 a uxiliary m ultiple phy r egister hcd. bits 15:11 of the auxiliary multiple phy register are 5 read-only bits that report the highest common denominator (hcd) result of the auto-negotiation process. immediately upon entering the link pass state after each reset or restart auto- negotiation, only 1 of these 5 bits is 1. the link pass state is identified by a 1 in bit 6 or 7 of this register. the hcd bits are reset to 0 every time auto-negotiation is restarted or the BCM5228 is reset. for their intended application, these bits uniquely identify the hcd only after the first link pass after reset or restart of a uto- negotiation. if the ability of the link partner is different on later link fault and subsequent renegotiations, more than one o f the above bits may be active. restart auto-negotiation . a self-clearing bit that allows the auto-negotiation process to be restarted, regardless of the current status of the state machine. for this bit to work, auto-negotiation must be enabled. writing a 1 to this bit restarts auto-negotiation. because the bit is self-clearing, it always returns a 0 when read. the operation of this bit is identical to bit 9 of the control register. auto-negotiation complete . this read-only bit returns a 1 after the auto-negotiation process has been completed. it remains 1 until the auto-negotiation process is restarted, a link fault occurs, or the chip is reset. if auto-negotiation is di sabled or the process is still in progress, the bit returns a 0. table 38: auxiliary multiple phy register (address 30d, 1eh) bit name r/w description default 15 hcd_tx_fdx ro 1 = auto-negotiation result is 100base-tx full-duplex 0 14 hcd_t4 ro 1 = auto-negotiation result is 100base-t4 0 13 hcd_tx ro 1 = auto-negotiation result is 100base-tx 0 12 hcd_10base-t_fdx ro 1 = auto-negotiation result is 10base-t full-duplex 0 11 hcd_10base-t ro 1 = auto-negotiation result is 10base-t 0 10:9 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ?? 00 8 restart auto-negotiation r/w (sc) 1 = restart auto-negotiation process 0 = no effect 0 7 auto-negotiation complete ro 1 = auto-negotiation process completed 0 = auto-negotiation process not completed 0 6 acknowledge complete ro 1 = auto-negotiation acknowledge completed 0 5 acknowledge detected ro 1 = auto-negotiation acknowledge detected 0 4 ability detect ro 1 = auto-negotiation waiting for lp ability 0 3 super isolate r/w 1 = super isolate mode 0 = normal operation 0 2 reserved a ?? 0 1 10base-t serial mode r/w 1 = enable 10base-t serial mode 0 = disable 10base-t serial mode 0 0 reserved a ?? 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation.
BCM5228 data sheet 7/12/04 broadcom corporation page 62 broadcom test register document 5228-ds09-405-r acknowledge complete. this read-only bit returns a 1 after the acknowledgment exchange portion of the auto-negotiation process has been completed and the arbitrator state machine has exited the acknowledge complete state. it remains this value until the auto-negotiation process is restarted, a link fault occurs, auto-negotiation is disabled, or the BCM5228 is res et. acknowledge detected. this read-only bit is set to 1 when the arbitrator state machine exits the acknowledge detect state. it remains high until the auto-negotiation process is restarted, or the BCM5228 is reset. ability detect. this read-only bit returns a 1 when the auto-negotiation state machine is in the ability detect state. it enters this state a specified time period after the auto-negotiation process begins, and exits after the first flp burst or link pulse s are detected from the link partner. this bit returns a 00 any time the auto-negotiation state machine is not in the ability det ect state. super isolate. writing a 1 to this bit places the BCM5228 into the super isolate mode. similar to the isolate mode, all rmii/ smii/s3mii inputs are ignored, and all rmii/smii/s3mii outputs are tri-stated. additionally, all link pulses are suppressed. this allows the BCM5228 to coexist with another phy on the same adapter card, with only one being activated at any time. see also ?super isolate mode? on page 26 . 10base-t serial mode. writing a 1 to bit 1 of the auxiliary mode register enables the 10base-t serial mode. in 10base-t serial mode, data packets traverse to the mac layer across only txd0 and rxd0 at a rate of 10 mhz. serial operation is not available in 100base-x mode. b roadcom t est r egister shadow register enable. writing a 1 to bit 7 of register 1fh allows r/w access to the shadow registers. table 39: broadcom test (address 31d, 1fh) bit name r/w description default 15:8 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ? ?00h 7 shadow register enable r/w 1 = enable shadow registers 1ah-1eh 0 = disable shadow registers 0 6 reserved a ? ?0 5 reserved a ? ?0 4:0 reserved a ? ?0bh note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation.
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r auxiliary mode 4 (phy 1) register (shadow register) page 63 a uxiliary m ode 4 (phy 1) r egister (s hadow r egister ) mii led select enable . enables configuration of led functions through mii register writes when this bit is set to a 1. otherwise, power-on reset configurations are in effect. parallel led3 select[1:0] . bit 7 and 6 select led output for the parallel led3 pin if mii led select enable is set to a 1. parallel led2 select[2:0] . bit 5 and 3 select led output for the parallel led2 pin if mii led select enable is set to a 1. parallel led1 select[2:0] . bit 2 and 0 select led output for the parallel led1 pin if mii led select enable is set to a 1. table 40: auxiliary mode 4 (phy 1) register (shadow register 26d, 1ah) bit name r/w description default 15:9 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ? ? 0011 000b 8 mii led select enable r/w 1 = enable led output selection through mii register 0 7:6 parallel led3 select[1:0] r/w configuration bits for led3 output. for details, see ?led modes? on page 29 . txer/led1[7:6] b b. status of txer/led1[7:0] during power-on reset determines the default values for parallel led3, led2 and led1 selects. 5:3 parallel led2 select[2:0] r/w configuration bits for led2 output. for details, see ?led modes? on page 29 . txer/led1[5:3] 2:0 parallel led1 select[2:0] r/w configuration bits for led1 output. for details, see ?led modes? on page 29 . txer/led1[2:0] note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1.
BCM5228 data sheet 7/12/04 broadcom corporation page 64 auxiliary mode 4 (phy 2) regist er (shadow register ) document 5228-ds09-405-r a uxiliary m ode 4 (phy 2) r egister (s hadow r egister ) serial bank 6 select[2:0] . if low-cost serial led mode is selected, these bits configure bank 6 led output on the serial led data stream sled_do. serial bank 5 select[2:0] . if low-cost serial led mode is selected, these bits configure bank 5 led output on the serial led data stream sled_do. serial bank 4 select [2:0] . if low-cost serial led mode is selected, these bits configure bank 4 led output on the serial led data stream sled_do. table 41: auxiliary mode 4 (phy 2) register (shadow register 26d, 1ah) bit name r/w description default 15:9 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ? ? 0011 000b 8:6 serial bank 6 select[2:0] r/w configuration bits for bank 6 output in low-cost serial led mode. for details, see ?led modes? on page 29 . 000 5:3 serial bank 5 select[2:0] r/w configuration bits for bank 5 output in low-cost serial led mode. for details, see ?led modes? on page 29 . 000 2:0 serial bank 4 select[2:0] r/w configuration bits for bank 4 output in low-cost serial led mode. for details, see ?led modes? on page 29 . 000 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1.
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r auxiliary mode 4 (phy 3) register (shadow register) page 65 a uxiliary m ode 4 (phy 3) r egister (s hadow r egister ) serial bank 3 select[2:0] . if low-cost serial led mode is selected, these bits configure bank 6 led output on serial led data stream sled_do. serial bank 2 select[2:0] . if low-cost serial led mode is selected, these bits configure bank 5 led output on serial led data stream sled_do. serial bank 1 select[2:0] . if low-cost serial led mode is selected, these bits configure bank 4 led output on serial led data stream sled_do. table 42: auxiliary mode 4 (phy 3) register (shadow register 26d, 1ah) bit name r/w description default 15:9 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ? ? 0011 000b 8:6 serial bank 3 select[2:0] r/w configuration bits for bank 3 output in low-cost serial led mode. for details, see ?led modes? on page 29 . 000 5:3 serial bank 2 select[2:0] r/w configuration bits for bank 2 output in low-cost serial led mode. for details, see ?led modes? on page 29 . 000 2:0 serial bank 1 select[2:0] r/w configuration bits for bank 1 output in low-cost serial led mode. for details, see ?led modes? on page 29 . 000 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1.
BCM5228 data sheet 7/12/04 broadcom corporation page 66 auxiliary status 2 register (shadow register) document 5228-ds09-405-r a uxiliary s tatus 2 r egister (s hadow r egister ) mlt3 detected . the BCM5228 returns a 1 in this bit whenever mlt3 signaling is detected. cable length 100x [2:0] . the BCM5228 provides the cable length for each port when a 100tx link is established. adc peak amplitude [5:0] . the BCM5228 returns the a to d converter?s 6-bit peak amplitude seen during this link. apd enable . when in normal mode, if this bit is set to a 1, the BCM5228 enters auto power-down mode. if this bit is set and the link is lost, the BCM5228 enters low power-down mode. when energy is detected, the device enters full power mode. otherwise, it wakes up after either 2.5 seconds or 5.0 seconds, as determined by the apd sleep timer bit. when the BCM5228 wakes up, it sends link pulses and also monitors energy. if the link partner?s energy is detected, the BCM5228 device continues to stay in wake-up mode for a duration determined by the apd wake-up timer before going to low power mode. apd sleep timer . this bit determines how long the BCM5228 stays in low power mode before waking up. if this bit is a 0, the BCM5228 device waits approximately 2.5 seconds before waking up. otherwise, it wakes up after approximately 5.0 seconds. table 43: auxiliary status 2 register (shadow register 27d, 1bh) bit name r/w description default 15 mlt3 detected r/o 1 = mlt3 detected 0 14:12 cable length 100x[2:0] r/o the BCM5228 shows the cable length in 20-meter increments, as shown in table 44 . 000 11:6 adc peak amplitude[5:0] r/o a to d peak amplitude seen 00h 5 apd enable r/w 0 = normal mode 1 = enable auto power-down mode 0 4 apd sleep timer r/w 0 = 2.5-second sleep before wake up 1= 5.0-second sleep before wake up 0 3:0 apd wake-up timer[3:0] r/w duration of wake up 0001 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1. table 44: cable length cable length 100x [2:0] cable length in meters 000 < 20 001 20 to <40 010 40 to <60 011 60 to < 80 100 80 to < 100 101 100 to < 120 110 120 to < 140 111 > 140
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r auxiliary status 3 register (shadow register) page 67 apd wake-up timer[3:0] . this counter determines how long the BCM5228 stays in wake-up mode before going to low power mode. this value is specified in 40-millisecond increments from 0 to 600 milliseconds. a value of 0 forces the BCM5228 to stay in low power mode indefinitely. in this case, the BCM5228 requires a hard reset to return to normal mode. a uxiliary s tatus 3 r egister (s hadow r egister ) noise[7:0] . the BCM5228 provides the current mean squared error value for noise when a valid link is established. fifo consumption[3:0] . the BCM5228 indicates the number of nibbles of fifo currently used. table 45: auxiliary status 3 register (shadow register 28d, 1ch) bit name r/w description default 15:8 noise [7:0] r/o current mean square error value, valid only if link is established 00h 7:4 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ? ? 000h 3:0 fifo consumption [3:0] r/o currently used number of nibbles in the receive fifo 0000 note: mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1.
BCM5228 data sheet 7/12/04 broadcom corporation page 68 auxiliary mode 3 register (shadow register) document 5228-ds09-405-r a uxiliary m ode 3 r egister (s hadow r egister ) fifo size select[3:0] . the BCM5228 indicates the current selection of receive fifo size using bit 3 through 0, as shown in table 47 . the size can also be determined by the extended fifo enable bit (register 10h, bit 2) and the jumbo packet fifo enable bit (register 1bh, bit 9) for backward compatibility with the 0.35-micron products. table 46: auxiliary mode 3 register (shadow register 29d, 1dh) bit name r/w description default 15:9 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ?? 0 8 reserved a ?? 0 7 reserved a ?? 0 6 reserved a ?? 0 5:4 reserved a ?? 0h 3:0 fifo size select [3:0] r/w currently-selected receive fifo size 4h note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll and lh clear after read operation. mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1. table 47: current receive fifo size fifo size select[3:0] receive fifo size in use (# of bits) 0000 12 0001 16 0010 20 0011 24 0100 28 0101 32 0110 36 0111 40 1000 44 1001 48 1010 52 1011 56 1100 60 1101 64
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r auxiliary status 4 register (shadow register) page 69 a uxiliary s tatus 4 r egister (s hadow r egister ) packet length counter[15:0] . the BCM5228 shows the number bytes in the last packet received. this is valid only when a valid link is established. table 48: auxiliary status 4 register (shadow register 30d, 1eh) bit name r/w description default 15:0 packet length counter[15:0] r/o number of bytes in the last received packet 0000h
BCM5228 data sheet 7/12/04 broadcom corporation page 70 timing and ac characteristics document 5228-ds09-405-r section 7: timing an d ac characteristics all digital output timing is specified at c l = 30 pf. output rise/fall times are measured between 10% and 90% of the output signal swing. input rise/fall times are measured between v il maximum and v ih minimum. output signal transitions are referenced to the midpoint of the output signal swing. input signal transitions are referenced to the midpoint between v il maximum and v ih minimum. figure 5: clock and reset timing table 49: clock timing parameter symbol min typ max unit ref_clk cycle time (50-mhz operation) ck_cycle ? 20 ? ns ref_clk cycle time (125-mhz operation) ck_cycle ? 8 ? ns ref_clk high/low time (50-mhz operation) ck_hi ck_lo 71013ns ref_clk high/low time (125-mhz operation) ck_hi ck_lo ?4?ns ref_clk rise/fall time (50-mhz operation) ck_edge ? ? 2 ns ref_clk rise/fall time (125-mhz operation) ck_edge ? ? 1 ns table 50: reset timing parameter symbol min typ max unit reset pulse length with stable ref_clk input reset_len 2 ? ? s activity after end of reset reset_wait 100 ? ? s reset rise/fall time reset_edge ? ? 10 ns ref_clk reset# normal phy begin here reset_len reset_wait ck_hi ck_cycle ck_edge ck_lo ck_edge activity can reset_edge reset_edge
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r timing and ac characteristics page 71 figure 6: rmii transmit packet timing table 51: rmii transmit timing parameter symbol min typ max unit ref_clk cycle time ref_clk ? 20 ? ns txen, tx_er, txd[1:0] setup time to ref_clk rising txen_setup 4 ? ? ns txen, tx_er, txd[1:0] hold time from ref_clk rising txen_hold 2 ? ? ns td after txen assert txen_tdata ? 89 ? ns txd to td steady state delay txd_tdata ? 95 ? ns note: txd[1:0] shall provide valid data for each ref_clk period while tx_en is asserted. as the ref_clk frequency is 10 times the data rate in 10mb/s mode, the value on txd[1:0] shall be valid such that txd[1:0] can be sampled every 10th cycle, regardless of the starting cycle within the group and yield the correct frame data. table 52: rmii receive timing parameter symbol min typ max unit ref_clk cycle time ref_clk ? 20 ? ns rxd[1:0], crs, dv, rx_er output delay from ref_clk rising ? 2 16 ns crs_dv assert after rd rx_crs_dv ? 124 ? ns crs_dv deassert after rd rx_crs_dv ? 164 ? ns crs_dv deassert after rd , valid eop rx_crs_dv_eop ? 237 ? ns note: as the ref_clk frequency is 10 times the data rate in 10 mbps mode, the value on rxd[1:0] is valid such that rxd[1:0] can be sampled every 10th cycle, regardless of th e starting cycle within the group and yield the correct frame data. the receiver accounts for differences between the local ref_clk and the recovered clock through use of sufficient elasticity buffering. the output delay has a load of 25 pf, which accommodates a pcb trace length of over 12 inches. 0 0 0 0 0 0 0 0 txd[1] txd[0] tx_en ref_clk 1 1 1 1 1111111111 xxxx xx x x x x x x 00000000 preamble data sfd
BCM5228 data sheet 7/12/04 broadcom corporation page 72 timing and ac characteristics document 5228-ds09-405-r figure 7: rmii receive packet timing figure 8: rmii receive packet with false carrier table 53: smii/s3mii timing parameter symbol min typ max unit stx (txd) setup (sclk rising) stx_setup 1.5 ? ? ns stx (txd) hold (sclk rising) stx_hold 1.0 ? ? ns sync (ssync) setup (sclk rising) sync_setup 1.5 ? ? ns sync (ssync) hold (sclk rising) sync_hold 1.0 ? ? ns srx (rxd) delay (sclk rising) srx_delay 2.0 ? 5.0 ns smii_rsync delay sync_delay 2.0 ? 5.0 ns note: sclk is ref_clk in smii mode sclk is smii_txc for s3mii stx sclk is smii_rxc for s3mii srx /j/ /k/ preamble sfd data 0 1 0 0 00 0 0 0 0 0 0 0 0 0000000 111111xx xxx0 0 x xxxxx x 1 rxd[1] rxd[0] crs_dv ref_clk 1 0 0 0 0 0 0000000 1 0 0 rxd[1] rxd[0] crs_dv ref_clk 11 0000000 11111111111 000000 false carrier detected
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r timing and ac characteristics page 73 figure 9: smii/s3mii timing table 54: auto-negotiation timing parameter symbol min typ max unit link test pulse width ? ? 100 ? ns flp burst interval ? 5.7 16 22.3 ms clock pulse to clock pulse ? 111 123 139 s clock pulse to data pulse (data = 1) ? 55.5 62.5 69.5 s table 55: led timing parameter symbol min typ max unit led on time (actled) ? ? 80 ? ms led off time (actled) ? ? 80 ? ms table 56: mii management data interface timing parameter symbol min typ max unit mdc cycle time ? 40 ? ? ns mdc high/low ? 20 ? ? ns mdc rise/fall time ? ? ? 10 ns mdio input setup time to mdc rising ? 10 ? ? ns mdio input hold time from mdc rising ? 10 ? ? ns mdio output delay from mdc rising ? 0 ? 30 ns sync sclk stx srx srx_delay stx_hold stx_setup sync_setup sync_hold tx_er tx_en txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 crs rx_dv rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7 sync_delay
BCM5228 data sheet 7/12/04 broadcom corporation page 74 timing and ac characteristics document 5228-ds09-405-r figure 10: management interface timing figure 11: management interface timi ng (with preamble suppression on) mdc mdc_fall mdio_hold mdio_setup mdc_rise mdc_cycle mdio_setup mdio_hold mdio_delay mdio (into BCM5228 ) mdio (from BCM5228 ) mdc skip skip d0 d1 hi-z (phy pull-up) idle s t mdio start of mdc/mdio cycle end of mdc/mdio cycle skip 2 mdc clocks between mdc/mdio cycles with preamble suppressed rmii register 1, bit 6 set to 1
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r timing and ac characteristics page 75
BCM5228 data sheet 7/12/04 broadcom corporation page 76 electrical characte ristics document 5228-ds09-405-r section 8: electrical characteristics table 57: absolute maximum ratings symbol parameter min max units v dd supply voltage gnd ? 0.3 2.75 v v i input voltage gnd ? 0.3 ovdd + 0.3 v i i input current ? 10 ma t stg storage temperature ? 40 +125 c v esd electrostatic discharge ? 1000 v note: these specifications indicate levels where permanent damage to the device can occur. functional operation is not guaranteed under these conditions. operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device. table 58: recommended operating conditions symbol parameter pins operating mode min max units v dd supply voltage ovdd ? 2.375 3.465 v v dd supply voltage avdd, dvdd, pllvddc, biasvdd ? 2.375 2.625 v v ih high-level input voltage all digital inputs ? 2.0 v v il low-level input voltage all digital inputs ? 0.8 v sd {1:8} 100base-fx 0.4 v v idiff differential input voltage sd {1:8} 100base-fx 150 ? mv v icm common mode input voltage rd {1:8} 100base-tx 1.85 2.05 v rd {1:8} , sd {1:8} 100base-fx 1.60 1.80 v t a ambient operating temperature ??070 c table 59: electrical characteristics symbol parameter pins conditions min typ max units i dd total supply current avdd, dvdd 100base-tx ? 839 892 ma ovdd 100base-tx ? 59 76 ma v oh high-level output voltage digital outputs i oh = ? 12 ma, ovdd = 3.3 v ovdd ? 0.5 ?? v digital outputs i oh = ? 12 ma, ovdd = 2.5 v ovdd ? 0.4 ?? v td {1:8} driving loaded magnetics module ? ? vdd + 1.5 v
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r electrical characteristics page 77 v ol low-level output voltage all digital outputs i ol = 8 ma ? ? 0.4 v td {1:8} driving loaded magnetics module dvdd ? 1.5 ?? v v odiff differential output voltage td {1:8} 100base-fx mode 400 ?? mv i i input current digital inputs with pull-up resistors v i = ovdd ? ? +100 a v i = dgnd ? ? -200 a digital inputs with pull-down resistors v i = ovdd ? ? +200 a v i = dgnd ? ? ?100 a all other digital inputs dgnd v i ovdd ?? 100 a i oz high-impedance output current all three-state outputs dgnd v o ovdd ??? a all open-drain outputs v o = ovdd ??? a v bias bias voltage vref, rdac ? 1.18 ? 1.30 v table 59: electrical characteristics (cont.) symbol parameter pins conditions min typ max units
BCM5228 data sheet 7/12/04 broadcom corporation page 78 mechanical information document 5228-ds09-405-r section 9: mechanical information figure 12: 208-pin pqfp package d1 d e1 e 1 seating plane a a1 a2 l b e r 1 2 r 2 1 c 1. drawings on this page are not to scale 2. all dimensions are in millimeters except where noted 3. foot length "l" is measured at gage plane, 0.25mm above the seating plane 4. seating plane is defined by three lowest lead tips 208-pin detail 3 4 h millimeter symbol min nom max a a1 a2 d d1 e e1 l e b c 0.25 3.39 30.35 27.90 30.35 27.90 0.30 0.50 bsc 0.15 0.22 0.30 0.60 0.75 28.00 28.10 30.60 30.85 28.00 28.10 30.60 30.85 3.49 3.59 0.50 4.10 0.13 h 0.102 r r 0.20 0.30 3 1 2 4 2 0 6 7 10 10 10 notes: 1 2 0.37 0.23 0.08
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r mechanical information page 79 figure 13: 256-pin fine pitch bga (fpbga) package top view a1 ball pad corner c0.20 m side view 6 seating plane x zy ?0.50 typ 5 x y 1.45p0.10 0.40p0.05 17.00 c0.08 m z 1.05p0.05 0.10 4x 17.00 0.15 z z 0.20 z bottom view (256 solder balls) 1 a1 ball pad corner 1.00 b d c e 2 3 4 5 1.00 ref a 1.00 ref 1.00 109 876 k j h g f 11 12 m l t p r 16 15 13 14 5 dimension is measured at the maximum solder ball diameter, parallel to primary datum z. the maximum allowable number of solder balls is 256. the maximum solder ball matrix size is 16 x 16. the basic solder ball grid pitch is 1.00. all dimensions and tolerances conform to asme y14.5m-1994. 4. 3. 2. 1. primary datum z and seating plane are defined by the spherical crowns of the solder balls. 6 n
BCM5228 data sheet 7/12/04 broadcom corporation page 80 packaging thermal characteristics document 5228-ds09-405-r section 10: packaging thermal characteristics theta jc for this package is 5.84c/w. the BCM5228b is designed and rated for a maximum junction temperature of 125c. theta jc for this package is 6.19c/w. the BCM5228f is designed and rated for a maximum junction temperature of 125c. theta jc for this package is 6.19c/w. the BCM5228u is designed and rated for a maximum junction temperature of 125c. table 60: theta ja vs. airflow for the BCM5228b (256 fpbga) package airflow (feet per minute) 0 100 200 400 600 theta ja (c/w) 19.02 16.70 15.85 14.84 14.16 table 61: theta ja vs. airflow for the BCM5228f (208 pqfp) package airflow (feet per minute) 0 100 200 400 600 theta ja (c/w) 16.35 13.96 13.09 12.21 11.70 table 62: theta ja vs. airflow for the BCM5228u (208 pqfp) package airflow (feet per minute) 0 100 200 400 600 theta ja (c/w) 16.35 13.96 13.09 12.21 11.70
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r packaging t hermal characteristics page 81
BCM5228 data sheet 7/12/04 broadcom corporation page 82 application examples document 5228-ds09-405-r section 11: application examples figure 14: smii application BCM5228 sclk 125 mhz 16 port mac rxd0{1:8} 8 8 txd0{1:8} rxd0{1:8} 8 8 ssync txd0{1:8} BCM5228
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r application examples page 83 figure 15: smii application us ing source synchronous signals BCM5228 sclk 125 mhz 16 port mac ssync rxd0 {1:8} smii_rxc 8 8 smii_txc txd0{1:8} smii_rsync smii_txc rxd0 {1:8} smii_rxc 8 8 ssync txd0{1:8} smii_rsync BCM5228
document 5228-ds09-405-r broadcom corporation 16215 alton parkway p.o. box 57013 irvine, ca 92619-7013 phone: 949-450-8700 fax: 949-450-8710 broadcom ? corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, f unction, or design. information furnished by broadcom corporation is believed to be accurate and reliable. however, broadcom corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any prod uct or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. BCM5228 data sheet 7/12/04
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r application examples page 85 figure 16: switch application BCM5228 50-mhz (rmii) mac rj45 magnetics rmii{7}/smii{7} rmii{8}/smii{8} ref_clk leds (1) rmii{2}/smii{2} rmii{1}/smii{1} td {2} rd {2} td {1} rd {1} td {7} rd{7} td{8} rd{8} 125-mhz (smii) mac mac mac rj45 (2) rj45 (7) rj45 (8)
BCM5228 data sheet 7/12/04 broadcom corporation page 86 application examples document 5228-ds09-405-r
data sheet BCM5228 7/12/04 broadcom corporation document 5228-ds09-405-r ordering information page 87 section 12: ordering information the BCM5228ba4ipb can operate at ?40 c to +85 c (?40 f to 185 f) if used with a heat sink (see the following for details) or equivalent: the following thermal data applies to the BCM5228ba4ipb with the heat sink previously described. part number package ambient temperature BCM5228ua4kpf 208 pqfp 0 c to 70 c (32 f to 158 f) BCM5228fa4kpf 208 pqfp 0 c to 70 c (32 f to 158 f) BCM5228ba4kpb 256 fbga 0 c to 70 c (32 f to 158 f) BCM5228ua4ipf 208 pqfp ?40 c to 85 c (?40 f to 185 f) BCM5228fa4ipf 208 pqfp ?40 c to 85 c (?40 f to 185 f) BCM5228ba4ipb 256 fpbga ?40 c to 70 c (?40 f to 158 f) note: a4 is the current revision number at the time of publication of this data sheet. manufacturer: wakefield engineering part number: 624-60ab, made of extruded aluminum, 21 mm 21 mm 15.2 mm pin-fin thermal interface: chomerics t410 double-sided thermal tape table 63: theta ja vs. airflow for the BCM5228b with heat sink airflow (feet per minute) 0 100 200 400 600 theta ja (c/w) 13.37 11.51 10.61 9.94 9.58
BCM5228 data sheet 7/12/04 broadcom corporation page 88 ordering information document 5228-ds09-405-r

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